From patchwork Mon Dec 4 17:53:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 844356 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yrCDd3wldz9t8J for ; Tue, 5 Dec 2017 04:54:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752491AbdLDRyH (ORCPT ); Mon, 4 Dec 2017 12:54:07 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3917 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751756AbdLDRyF (ORCPT ); Mon, 4 Dec 2017 12:54:05 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Mon, 04 Dec 2017 09:53:56 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 04 Dec 2017 09:54:05 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 04 Dec 2017 09:54:05 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Mon, 4 Dec 2017 17:54:04 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Mon, 4 Dec 2017 17:54:04 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.45]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 04 Dec 2017 09:54:04 -0800 From: Vidya Sagar To: , CC: , , , , , , Subject: [PATCH V3 2/2] ARM64: tegra: limit PCIe config space mapping to 4K for T186 Date: Mon, 4 Dec 2017 23:23:50 +0530 Message-ID: <1512410030-21038-3-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1512410030-21038-1-git-send-email-vidyas@nvidia.com> References: <1512410030-21038-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org reduces PCIe config space mapping size from its current 256MB to 4K to have only 4K of virtual memory mapping and to be in line with driver implementation Signed-off-by: Vidya Sagar --- V3: * no change in this patch arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 46d1f287fb0f..62fa3bef3e18 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -363,7 +363,7 @@ device_type = "pci"; reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ - 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + 0x0 0x40000000 0x0 0x00001000>; /* configuration space */ reg-names = "pads", "afi", "cs"; interrupts = , /* controller interrupt */ @@ -381,9 +381,9 @@ ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ - 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ - 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ - 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + 0x81000000 0 0x0 0x0 0x40001000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x40100000 0x0 0x40100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x48000000 0x0 0x48000000 0 0x38000000>; /* prefetchable memory (896 MiB) */ clocks = <&bpmp TEGRA186_CLK_AFI>, <&bpmp TEGRA186_CLK_PCIE>,