From patchwork Sat Nov 25 19:32:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manikanta Maddireddy X-Patchwork-Id: 841284 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3ykjry74F0z9s71 for ; Sun, 26 Nov 2017 06:33:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751716AbdKYTdA (ORCPT ); Sat, 25 Nov 2017 14:33:00 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19033 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751634AbdKYTcx (ORCPT ); Sat, 25 Nov 2017 14:32:53 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sat, 25 Nov 2017 11:32:55 -0800 Received: from HQMAIL107.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sat, 25 Nov 2017 11:32:53 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sat, 25 Nov 2017 11:32:53 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:52 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Sat, 25 Nov 2017 19:32:52 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via Frontend Transport; Sat, 25 Nov 2017 19:32:52 +0000 Received: from manikanta-pc.nvidia.com (Not Verified[10.19.65.28]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 25 Nov 2017 11:32:51 -0800 From: Manikanta Maddireddy To: , , , , , , CC: , , , , , , Manikanta Maddireddy Subject: [PATCH V2 8/9] PCI: tegra: Broadcast PME_turn_Off message before link goes to L2 Date: Sun, 26 Nov 2017 01:02:12 +0530 Message-ID: <1511638333-22951-9-git-send-email-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> References: <1511638333-22951-1-git-send-email-mmaddireddy@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Per PCIe r3.0, sec 5.3.3.2.1, PCIe root port shoould broadcast PME_turn_Off message before PCIe link goes to L2. PME_turn_Off broadcast mechanism is implemented in AFI module. Each Tegra PCIe root port has its own PME_turn_Off and PME_TO_Ack bitmap in AFI_PME register, program this register to broadcast PME_turn_Off message. Signed-off-by: Manikanta Maddireddy --- V2: * no change in this patch drivers/pci/host/pci-tegra.c | 76 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index bbc2807bcd4a..b380958a3deb 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -155,6 +155,8 @@ #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) #define AFI_INTR_EN_PRSNT_SENSE (1 << 8) +#define AFI_PCIE_PME 0xf0 + #define AFI_PCIE_CONFIG 0x0f8 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1)) #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe @@ -315,6 +317,7 @@ #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */ #define LINK_RETRAIN_TIMEOUT 100000 +#define PME_ACK_TIMEOUT 10000 struct tegra_msi { struct msi_controller chip; @@ -1503,6 +1506,76 @@ static int tegra_pcie_put_resources(struct tegra_pcie *pcie) return 0; } +static inline u32 get_pme_turnoff_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 0; + case 1: + ret = 8; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 16; + else + ret = 12; + } + return ret; +} + +static inline u32 get_pme_ack_bitmap(struct tegra_pcie_port *port) +{ + struct device *dev = port->pcie->dev; + struct device_node *np = dev->of_node; + int ret = 0; + + switch (port->index) { + case 0: + ret = 5; + case 1: + ret = 10; + case 2: + if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) + ret = 18; + else + ret = 14; + } + return ret; +} + +static void tegra_pcie_pme_turnoff(struct tegra_pcie_port *port) +{ + struct tegra_pcie *pcie = port->pcie; + ktime_t deadline; + unsigned int data; + + data = afi_readl(pcie, AFI_PCIE_PME); + data |= (0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); + + deadline = ktime_add_us(ktime_get(), PME_ACK_TIMEOUT); + do { + data = afi_readl(pcie, AFI_PCIE_PME); + data &= (0x1 << get_pme_ack_bitmap(port)); + udelay(1); + if (ktime_after(ktime_get(), deadline)) + break; + } while (!data); + + if (data) + dev_err(pcie->dev, "PME Ack is not receieved on port: %d\n", + port->index); + + usleep_range(10000, 11000); + + data = afi_readl(pcie, AFI_PCIE_PME); + data &= ~(0x1 << get_pme_turnoff_bitmap(port)); + afi_writel(pcie, data, AFI_PCIE_PME); +} + static int tegra_msi_alloc(struct tegra_msi *chip) { int msi; @@ -2828,6 +2901,7 @@ static int tegra_pcie_remove(struct platform_device *pdev) { struct tegra_pcie *pcie = platform_get_drvdata(pdev); struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie); + struct tegra_pcie_port *port, *tmp; if (IS_ENABLED(CONFIG_DEBUG_FS)) tegra_pcie_debugfs_exit(pcie); @@ -2835,6 +2909,8 @@ static int tegra_pcie_remove(struct platform_device *pdev) pci_remove_root_bus(host->bus); if (IS_ENABLED(CONFIG_PCI_MSI)) tegra_pcie_disable_msi(pcie); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + tegra_pcie_pme_turnoff(port); tegra_pcie_disable_ports(pcie); tegra_pcie_free_resources(pcie); tegra_pcie_disable_controller(pcie);