From patchwork Thu Nov 16 15:33:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 838635 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yd4yX42YQz9ryv for ; Fri, 17 Nov 2017 02:33:24 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759935AbdKPPdX (ORCPT ); Thu, 16 Nov 2017 10:33:23 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:13408 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759924AbdKPPdV (ORCPT ); Thu, 16 Nov 2017 10:33:21 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 16 Nov 2017 07:33:21 -0800 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 16 Nov 2017 07:33:21 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 16 Nov 2017 07:33:21 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 16 Nov 2017 15:33:20 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 16 Nov 2017 15:33:15 +0000 Received: from tbergstrom-lnx.Nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id B02F2F80887; Thu, 16 Nov 2017 17:33:12 +0200 (EET) From: Peter De Schrijver To: , CC: Peter De Schrijver Subject: [PATCH 8/8] arm64: dts: nvidia: Tegra210 CPU clock definition Date: Thu, 16 Nov 2017 17:33:09 +0200 Message-ID: <1510846389-28712-9-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510846389-28712-1-git-send-email-pdeschrijver@nvidia.com> References: <1510846389-28712-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Signed-off-by: Peter De Schrijver --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 813b9d8..c8d14d4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1230,6 +1230,13 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT_CPU>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + /* FIXME: what's the actual transition time? */ + clock-latency = <300000>; }; cpu@1 {