From patchwork Thu Nov 16 15:29:55 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 838625 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yd4tl2R8jz9s7M for ; Fri, 17 Nov 2017 02:30:07 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753334AbdKPPaG (ORCPT ); Thu, 16 Nov 2017 10:30:06 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6501 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750905AbdKPPaE (ORCPT ); Thu, 16 Nov 2017 10:30:04 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 16 Nov 2017 07:30:02 -0800 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 16 Nov 2017 07:30:03 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 16 Nov 2017 07:30:03 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 16 Nov 2017 15:30:03 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Thu, 16 Nov 2017 15:29:58 +0000 Received: from tbergstrom-lnx.Nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 489AFF8004C; Thu, 16 Nov 2017 17:29:58 +0200 (EET) From: Peter De Schrijver To: , CC: Peter De Schrijver Subject: [PATCH v2 4/4] soc/tegra: pmc: apply MBIST work around fo Tegra210 Date: Thu, 16 Nov 2017 17:29:55 +0200 Message-ID: <1510846195-28555-5-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510846195-28555-1-git-send-email-pdeschrijver@nvidia.com> References: <1510846195-28555-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Apply the memory built-in self test work around when ungating certain Tegra210 power domains. Signed-off-by: Peter De Schrijver --- drivers/soc/tegra/pmc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 0453ff6..4c0582d 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -142,6 +142,7 @@ struct tegra_pmc_soc { bool has_tsense_reset; bool has_gpu_clamps; + bool needs_mbist_war; const struct tegra_io_pad_soc *io_pads; unsigned int num_io_pads; @@ -411,6 +412,9 @@ static int tegra_powergate_power_up(struct tegra_powergate *pg, usleep_range(10, 20); + if (pg->pmc->soc->needs_mbist_war) + tegra210_handle_mbist_war(pg->id); + if (disable_clocks) tegra_powergate_disable_clocks(pg); @@ -1712,6 +1716,7 @@ static int tegra_pmc_resume(struct device *dev) .cpu_powergates = tegra210_cpu_powergates, .has_tsense_reset = true, .has_gpu_clamps = true, + .needs_mbist_war = true, .num_io_pads = ARRAY_SIZE(tegra210_io_pads), .io_pads = tegra210_io_pads, };