From patchwork Wed Mar 22 17:00:56 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 742208 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vpGFM45MFz9s7b for ; Thu, 23 Mar 2017 04:02:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935563AbdCVRCL (ORCPT ); Wed, 22 Mar 2017 13:02:11 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:19119 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935494AbdCVRBZ (ORCPT ); Wed, 22 Mar 2017 13:01:25 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 22 Mar 2017 10:00:38 -0700 Received: from HQMAIL104.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 22 Mar 2017 10:01:11 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 22 Mar 2017 10:01:11 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 22 Mar 2017 17:01:11 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Wed, 22 Mar 2017 17:01:11 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.151]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 22 Mar 2017 10:01:11 -0700 From: Jon Hunter To: Thierry Reding CC: Russell King , Rob Herring , Mark Rutland , , , , Jon Hunter Subject: [PATCH V2 5/5] soc/tegra: Add initial flowctrl support for Tegra132/210 Date: Wed, 22 Mar 2017 17:00:56 +0000 Message-ID: <1490202056-13040-6-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490202056-13040-1-git-send-email-jonathanh@nvidia.com> References: <1490202056-13040-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra132 and Tegra210 support the flowctrl module and so add initial support for these devices. Please note that Tegra186 does not support the flowctrl module, so update the initialisation function such that we do not fall back and attempt to map the 'hardcoded' address range for Tegra186. Furthermore 64-bit Tegra devices have always had the flowctrl node defined in their device-tree and so only use the 'hardcoded' addresses for 32-bit Tegra devices. Signed-off-by: Jon Hunter --- drivers/soc/tegra/Kconfig | 2 ++ drivers/soc/tegra/flowctrl.c | 31 +++++++++++++++++++++---------- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index c7e8ddfb574e..dcf088db40b6 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -63,6 +63,7 @@ if ARM64 config ARCH_TEGRA_132_SOC bool "NVIDIA Tegra132 SoC" select PINCTRL_TEGRA124 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for NVIDIA Tegra132 SoC, based on the Denver @@ -73,6 +74,7 @@ config ARCH_TEGRA_132_SOC config ARCH_TEGRA_210_SOC bool "NVIDIA Tegra210 SoC" select PINCTRL_TEGRA210 + select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, diff --git a/drivers/soc/tegra/flowctrl.c b/drivers/soc/tegra/flowctrl.c index 25eddfc8475d..0e345c05fc65 100644 --- a/drivers/soc/tegra/flowctrl.c +++ b/drivers/soc/tegra/flowctrl.c @@ -165,6 +165,7 @@ static int tegra_flowctrl_probe(struct platform_device *pdev) } static const struct of_device_id tegra_flowctrl_match[] = { + { .compatible = "nvidia,tegra210-flowctrl" }, { .compatible = "nvidia,tegra124-flowctrl" }, { .compatible = "nvidia,tegra114-flowctrl" }, { .compatible = "nvidia,tegra30-flowctrl" }, @@ -184,9 +185,7 @@ builtin_platform_driver(tegra_flowctrl_driver); static int __init tegra_flowctrl_init(void) { - /* hardcoded fallback if device tree node is missing */ - unsigned long base = 0x60007000; - unsigned long size = SZ_4K; + struct resource res; struct device_node *np; if (!soc_is_tegra()) @@ -194,17 +193,29 @@ static int __init tegra_flowctrl_init(void) np = of_find_matching_node(NULL, tegra_flowctrl_match); if (np) { - struct resource res; - - if (of_address_to_resource(np, 0, &res) == 0) { - size = resource_size(&res); - base = res.start; + if (of_address_to_resource(np, 0, &res) < 0) { + pr_err("failed to get flowctrl register\n"); + return -ENXIO; } - of_node_put(np); + } else if (IS_ENABLED(CONFIG_ARM)) { + /* + * Hardcoded fallback for 32-bit Tegra + * devices if device tree node is missing. + */ + res.start = 0x60007000; + res.end = 0x60007fff; + res.flags = IORESOURCE_MEM; + } else { + /* + * At this point we're running on a Tegra, + * that doesn't support the flow controller + * (eg. Tegra186), so just return. + */ + return 0; } - tegra_flowctrl_base = ioremap_nocache(base, size); + tegra_flowctrl_base = ioremap_nocache(res.start, resource_size(&res)); if (!tegra_flowctrl_base) return -ENXIO;