From patchwork Wed Nov 2 09:09:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 690334 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3t82kp1hbtz9tkk for ; Wed, 2 Nov 2016 20:25:22 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755229AbcKBJZH (ORCPT ); Wed, 2 Nov 2016 05:25:07 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:39563 "EHLO hkmmgate102.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754499AbcKBJZE (ORCPT ); Wed, 2 Nov 2016 05:25:04 -0400 Received: from hkpgpgate102.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate102.nvidia.com id ; Wed, 02 Nov 2016 17:24:03 +0800 Received: from HKMAIL103.nvidia.com ([10.18.67.137]) by hkpgpgate102.nvidia.com (PGP Universal service); Wed, 02 Nov 2016 02:25:01 -0700 X-PGP-Universal: processed; by hkpgpgate102.nvidia.com on Wed, 02 Nov 2016 02:25:01 -0700 Received: from DRBGMAIL101.nvidia.com (10.18.16.20) by HKMAIL103.nvidia.com (10.18.16.12) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 2 Nov 2016 09:25:00 +0000 Received: from HQMAIL104.nvidia.com (172.18.146.11) by DRBGMAIL101.nvidia.com (10.18.16.20) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 2 Nov 2016 09:24:59 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3 via Frontend Transport; Wed, 2 Nov 2016 09:24:55 +0000 From: Laxman Dewangan To: , , , , CC: , , , , , , "Laxman Dewangan" Subject: [PATCH 1/2] pinctrl: tegra: Add DT binding for io pads control Date: Wed, 2 Nov 2016 14:39:01 +0530 Message-ID: <1478077742-25437-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1478077742-25437-1-git-send-email-ldewangan@nvidia.com> References: <1478077742-25437-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA Tegra124 and later SoCs support the multi-voltage level and low power state of some of its IO pads. The IO pads can work in the voltage of the 1.8V and 3.3V of IO power rail sources. When IO interface are not used then IO pads can be configure in low power state to reduce the power from that IO pads. On Tegra124, the IO power rail source is auto detected by SoC and hence it is only require to configure in low power mode if IO pads are not used. On T210 onwards, the auto-detection is removed from SoC and hence SW must configure the PMC register explicitly to set proper voltage in IO pads based on IO rail power source voltage. Add DT binding document for detailing the DT properties for configuring IO pads voltage levels and its power state. Signed-off-by: Laxman Dewangan --- On top of the branch from Thierry's T186 work https://github.com/thierryreding/linux/tree/tegra186 .../bindings/pinctrl/nvidia,tegra-io-pad.txt | 112 +++++++++++++++++++++ include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h | 21 ++++ 2 files changed, 133 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt create mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt new file mode 100644 index 0000000..15cd21c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt @@ -0,0 +1,112 @@ +NVIDIA Tegra PMC IO pad controller + +NVIDIA Tegra124 and later SoCs support the multi-voltage level and +low power state of some of its IO pads. The IO pads can work in +the voltage of the 1.8V and 3.3V of IO power rail sources. When IO +interface are not used then IO pads can be configure in low power +state to reduce the power from that IO pads. + +On Tegra124, the IO power rail source is auto detected by SoC and hence +it is only require to configure in low power mode if IO pads are not +used. + +On T210 onwards, the auto-detection is removed from SoC and hence SW +must configure the PMC register explicitly to set proper voltage in +IO pads based on IO rail power source voltage. + +The voltage configurations and low power state of IO pads should be done +in boot if it is not going to change other wise dynamically based on IO +rail voltage on that IO pads and usage of IO pads + +The DT property of the io pads must be under the node of pmc i.e. +pmc@7000e400 for Tegra124 onwards. + +Please refer to in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +Tegra's pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for an +IO pads, or a list of IO pads. This configuration can include the voltage and +power enable/disable control + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. Each subnode only affects those +parameters that are explicitly listed. Unspecified is represented as an absent +property, + +See the TRM to determine which properties and values apply to each IO pads. +Macro values for property values are defined in + + +The voltage supported on the pads are 1.8V and 3.3V. The enums are defined as: + For 1.8V, use TEGRA_IO_PAD_POWER_SOURCE_1800000UV + For 3.3V, use TEGRA_IO_PAD_POWER_SOURCE_3300000UV + +Required subnode-properties: +========================== +- pins : An array of strings. Each string contains the name of an IO pads. Valid + values for these names are listed below. + +Optional subnode-properties: +========================== +-nvidia,power-source-voltage: Integer. The voltage level of IO pads. The + valid values are 1.8V and 3.3V. Macros are + defined for these voltage levels in + + Use TEGRA_IO_PAD_POWER_SOURCE_1800000UV for 1.8V + Use TEGRA_IO_PAD_POWER_SOURCE_3300000UV for 3.3V + + All IO pads do not support the 1.8V/3.3V + configurations. Valid values for "pins" are + audio-hv, dmic, gpio, sdmmc1, sdmmc3, spi-hv. + +Other than above, following properties are supported from generic pin +configuration explained in . +low-power-enable: enable low power mode. +low-power-disable: disable low power mode. + +Valid values for pin for T124 are: + audio, bb, cam, comp, csia, csib, csie, dsi, dsib, dsic, dsid, hdmi, + hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, + pex-ctrl, sdmmc1, sdmmc3, sdmmc4, sys-ddc, uart, usb0, usb1, usb2, + usb-bias + + All above pins support low power mode. + +Valid values for pin for T210 are: + audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, + dbg, debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, + gpio, hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, + pex-ctrl, sdmmc1, sdmmc3, spi, spi-hv, uart, usb-bias, usb0, + usb1, usb2, usb3. + + All above pins support low power mode. However, all IO pads do not + support the 1.8V/3.3V configurations. Valid values for + nvidia,io-pad-voltage are: + audio, audio-hv, cam, dbg, dmic, gpio, pex-ctrl, sdmmc1, sdmmc3, + spi, spi-hv,uart + +Example: + #include + pmc@7000e400 { + + pinctrl-names = "default"; + pinctrl-0 = <&tegra_io_pad_volt_default>; + tegra_io_pad_volt_default: common { + audio-hv { + pins = "audio-hv"; + nvidia,power-source-voltage = ; + }; + + gpio { + pins = "gpio"; + invidia,power-source-voltage = ; + }; + + audio { + pins = "audio", "dmic", "sdmmc1", "sdmmc3"; + low-power-enable; + }; + }; + }; diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h new file mode 100644 index 0000000..ae55768 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h @@ -0,0 +1,21 @@ +/* + * pinctrl-tegra-io-pad.h: Provides constants for Tegra IO pads + * pinctrl bindings. + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H +#define _DT_BINDINGS_PINCTRL_TEGRA_IO_PAD_H + +/* Power source voltage of IO pads. */ +#define TEGRA_IO_PAD_POWER_SOURCE_1800000UV 0 +#define TEGRA_IO_PAD_POWER_SOURCE_3300000UV 1 + +#endif