From patchwork Tue Sep 20 10:28:07 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 672193 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sdfBb62Mbz9sxS for ; Tue, 20 Sep 2016 20:29:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753859AbcITK2h (ORCPT ); Tue, 20 Sep 2016 06:28:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:18753 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753742AbcITK2d (ORCPT ); Tue, 20 Sep 2016 06:28:33 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 20 Sep 2016 03:28:29 -0700 Received: from HQMAIL103.nvidia.com ([172.20.187.11]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 20 Sep 2016 03:22:55 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 20 Sep 2016 03:22:55 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 20 Sep 2016 10:27:58 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 20 Sep 2016 10:27:58 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.118]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 20 Sep 2016 03:27:58 -0700 From: Jon Hunter To: "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson CC: , , , Jon Hunter Subject: [RFC PATCH 3/3] dt-bindings: Add support for devices with multiple PM domains Date: Tue, 20 Sep 2016 11:28:07 +0100 Message-ID: <1474367287-10402-4-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1474367287-10402-1-git-send-email-jonathanh@nvidia.com> References: <1474367287-10402-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Now that the generic PM domain framework supports devices that require multiple PM domains, update the device-tree binding for generic PM domains to state that one or more PM domain is permitted for a device. Signed-off-by: Jon Hunter --- Documentation/devicetree/bindings/power/power_domain.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt index 025b5e7df61c..12131159b605 100644 --- a/Documentation/devicetree/bindings/power/power_domain.txt +++ b/Documentation/devicetree/bindings/power/power_domain.txt @@ -20,8 +20,9 @@ Required properties: as specified by device tree binding documentation of particular provider. Optional properties: - - power-domains : A phandle and PM domain specifier as defined by bindings of - the power controller specified by phandle. + - power-domains : An array of one or more PM domain specifiers (defined by the + bindings of the PM domain provider) for each PM domain that + is required by the device. Some power domains might be powered from another power domain (or have other hardware specific dependencies). For representing such dependency a standard PM domain consumer binding is used. When provided, all domains