From patchwork Thu Aug 11 01:13:36 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 657983 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s8qlQ0sQvz9sxb for ; Thu, 11 Aug 2016 11:13:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751505AbcHKBNS (ORCPT ); Wed, 10 Aug 2016 21:13:18 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12141 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751124AbcHKBNS (ORCPT ); Wed, 10 Aug 2016 21:13:18 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 10 Aug 2016 18:13:18 -0700 Received: from HQMAIL101.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 10 Aug 2016 18:09:54 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 10 Aug 2016 18:09:54 -0700 Received: from HQMAIL110.nvidia.com (172.18.146.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 11 Aug 2016 01:13:16 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by hqmail110.nvidia.com (172.18.146.15) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 11 Aug 2016 01:13:16 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 11 Aug 2016 01:13:15 +0000 Received: from krait.nvidia.com (Not Verified[10.19.41.246]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 10 Aug 2016 18:13:15 -0700 From: Vince Hsu To: , , , , CC: , Vince Hsu Subject: [PATCH V2] soc/tegra: pmc: Fix incorrect DPD request Date: Thu, 11 Aug 2016 09:13:36 +0800 Message-ID: <1470878016-6098-1-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Reading the DPD_REQ & DPD2_REQ registers returns the previous requests. If we sets the current request bit with the returned value, then other pads will be turned on or off unexpectedly. Signed-off-by: Vince Hsu Reviewed-by: Jon Hunter --- Hi, I did not notice Laxman had a series[1] which also touched pmc code, and it seems the series isn't merged yet. Should I rebase this patch on it? Thanks, Vince drivers/soc/tegra/pmc.c | 28 ++++++++-------------------- 1 file changed, 8 insertions(+), 20 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 71c834f3847e..7792ed88d80b 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -967,8 +967,8 @@ static void tegra_io_rail_unprepare(void) int tegra_io_rail_power_on(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; int err; mutex_lock(&pmc->powergates_lock); @@ -977,15 +977,9 @@ int tegra_io_rail_power_on(unsigned int id) if (err) goto error; - mask = 1 << bit; + tegra_pmc_writel(IO_DPD_REQ_CODE_OFF | BIT(bit), request); - value = tegra_pmc_readl(request); - value |= mask; - value &= ~IO_DPD_REQ_CODE_MASK; - value |= IO_DPD_REQ_CODE_OFF; - tegra_pmc_writel(value, request); - - err = tegra_io_rail_poll(status, mask, 0, 250); + err = tegra_io_rail_poll(status, BIT(bit), 0, 250); if (err) { pr_info("tegra_io_rail_poll() failed: %d\n", err); goto error; @@ -1002,8 +996,8 @@ EXPORT_SYMBOL(tegra_io_rail_power_on); int tegra_io_rail_power_off(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; int err; mutex_lock(&pmc->powergates_lock); @@ -1014,15 +1008,9 @@ int tegra_io_rail_power_off(unsigned int id) goto error; } - mask = 1 << bit; - - value = tegra_pmc_readl(request); - value |= mask; - value &= ~IO_DPD_REQ_CODE_MASK; - value |= IO_DPD_REQ_CODE_ON; - tegra_pmc_writel(value, request); + tegra_pmc_writel(IO_DPD_REQ_CODE_ON | BIT(bit), request); - err = tegra_io_rail_poll(status, mask, mask, 250); + err = tegra_io_rail_poll(status, BIT(bit), BIT(bit), 250); if (err) goto error;