From patchwork Tue Aug 2 10:34:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 654641 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s3XfG47tnz9t3M for ; Tue, 2 Aug 2016 20:35:34 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751341AbcHBKfQ (ORCPT ); Tue, 2 Aug 2016 06:35:16 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5611 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752946AbcHBKfH (ORCPT ); Tue, 2 Aug 2016 06:35:07 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 02 Aug 2016 03:35:01 -0700 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 02 Aug 2016 03:32:10 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 02 Aug 2016 03:32:10 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 2 Aug 2016 10:35:03 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 2 Aug 2016 10:35:03 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.26.11.39]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 02 Aug 2016 03:34:57 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , Jon Hunter Subject: [PATCH 4/4] arm64: tegra: Add clock and reset names for audio powergate Date: Tue, 2 Aug 2016 11:34:29 +0100 Message-ID: <1470134069-12178-5-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> References: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add the clock and reset names for the Tegra210 Audio powergate. Please note that these are not currently used, but added from completeness and to be consistent with the other powergate nodes. Signed-off-by: Jon Hunter --- We added the clock and resets names for the XUSB partitions and so I thought we should do the same for the Audio. Should I update the binding documentation to say these should be provided? Currently it does not state these are required. If we do update the binding doc, I was not entirely sure what to put in the description for these properties. Typically the clock and reset names would be fixed for a device, but here we are not using them and so there are no fixed names. arch/arm64/boot/dts/nvidia/tegra210.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index c4cfdcf60d26..92e987acc551 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -644,7 +644,9 @@ pd_audio: aud { clocks = <&tegra_car TEGRA210_CLK_APE>, <&tegra_car TEGRA210_CLK_APB2APE>; + clock-names = "ape", "apb2ape"; resets = <&tegra_car 198>; + reset-names = "ape"; #power-domain-cells = <0>; };