From patchwork Tue Aug 2 10:34:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 654640 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s3XfF28qTz9t3M for ; Tue, 2 Aug 2016 20:35:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753363AbcHBKfO (ORCPT ); Tue, 2 Aug 2016 06:35:14 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:2005 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752335AbcHBKfH (ORCPT ); Tue, 2 Aug 2016 06:35:07 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 02 Aug 2016 03:34:47 -0700 Received: from HQMAIL108.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 02 Aug 2016 03:31:50 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 02 Aug 2016 03:31:50 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 2 Aug 2016 10:34:50 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 2 Aug 2016 10:34:50 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.26.11.39]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 02 Aug 2016 03:34:48 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , Jon Hunter Subject: [PATCH 3/4] clk: tegra: Correct bit width for PMC output clock mux Date: Tue, 2 Aug 2016 11:34:28 +0100 Message-ID: <1470134069-12178-4-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> References: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The bit field for setting the clock mux for the PMC output clocks is a 2-bit field and has always been a 2-bit field for all Tegra devices that have these clocks (starting with Tegra30). However, the PMC clock driver incorrectly specifies that this bit field is 3 bits wide and this causes other bits in the register to be over-written when setting up the mux. Therefore, correct the width for PMC clock mux to prevent over-writing other fields. Signed-off-by: Jon Hunter --- I did not bother marking this for stable because it has been around for such a long time I don't think that this has caused any problems. I only stumbled across this when dumping the register contents during some testing. Nonetheless we should correct this. drivers/clk/tegra/clk-tegra-pmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra-pmc.c b/drivers/clk/tegra/clk-tegra-pmc.c index 91377abfefa1..36469a2ca385 100644 --- a/drivers/clk/tegra/clk-tegra-pmc.c +++ b/drivers/clk/tegra/clk-tegra-pmc.c @@ -97,7 +97,7 @@ void __init tegra_pmc_clk_init(void __iomem *pmc_base, clk = clk_register_mux(NULL, data->mux_name, data->parents, data->num_parents, CLK_SET_RATE_NO_REPARENT, pmc_base + PMC_CLK_OUT_CNTRL, data->mux_shift, - 3, 0, &clk_out_lock); + 2, 0, &clk_out_lock); *dt_clk = clk;