[RFC,3/6] dt/bindings: Add bindings for Tegra20/30 NOR bus driver

From: Mirza Krak <mirza.krak@gmail.com>

Document the devicetree bindings for NOR bus driver found on Tegra20 and
Tegra30 SOCs

Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
---
 .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
 1 file changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt

On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
> 
> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> Tegra30 SOCs
> 
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> ---
>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> 
> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> new file mode 100644
> index 0000000..9ee4a66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> @@ -0,0 +1,73 @@
> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> +
> +The NOR controller supports a number of memory types, including synchronous NOR,
> +asynchronous NOR, and other flash memories with similar interfaces, such as
> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> +CAN chips, Wi-Fi chips etc.
> +
> +The actual devices are instantiated from the child nodes of a NOR node.
> +
> +Required properties:
> +
> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> + - reg: Should contain NOR controller registers location and length.
> + - clocks: Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> + - resets : Must contain an entry for each entry in reset-names.
> +   See ../reset/reset.txt for details.
> + - reset-names : Must include the following entries:
> +  - nor
> + - #address-cells: Must be set to 2 to allow memory address translation
> + - #size-cells:	Must be set to 1 to allow CS address passing
> + - ranges: Must be set up to reflect the memory layout with four integer
> + 		values for each chip-select line in use.
> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> +
> +Note that the NOR controller does not have any internal chip-select address
> +decoding and if you want to access multiple devices external chip-select
> +decoding must be provided.

Then what are the 2 chip selects in ranges?

Rob
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2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>> Tegra30 SOCs
>>
>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>> ---
>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>>  1 file changed, 73 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>
>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> new file mode 100644
>> index 0000000..9ee4a66
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> @@ -0,0 +1,73 @@
>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
>> +
>> +The NOR controller supports a number of memory types, including synchronous NOR,
>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>> +CAN chips, Wi-Fi chips etc.
>> +
>> +The actual devices are instantiated from the child nodes of a NOR node.
>> +
>> +Required properties:
>> +
>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>> + - reg: Should contain NOR controller registers location and length.
>> + - clocks: Must contain one entry, for the module clock.
>> +   See ../clocks/clock-bindings.txt for details.
>> + - resets : Must contain an entry for each entry in reset-names.
>> +   See ../reset/reset.txt for details.
>> + - reset-names : Must include the following entries:
>> +  - nor
>> + - #address-cells: Must be set to 2 to allow memory address translation
>> + - #size-cells:      Must be set to 1 to allow CS address passing
>> + - ranges: Must be set up to reflect the memory layout with four integer
>> +             values for each chip-select line in use.
>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>> +
>> +Note that the NOR controller does not have any internal chip-select address
>> +decoding and if you want to access multiple devices external chip-select
>> +decoding must be provided.
>
> Then what are the 2 chip selects in ranges?
>
> Rob

Those two chip selects are actually a representation of a external
decoding logic based on what we use on our board. Even though it the
NOR controller only supports one single chip select I wanted to give
an example on how one could create more chip-selects with an external
logic and what it would look like in the device tree representation.

I realize that the bindings should include above explanation or
something similar.

On 19/07/16 14:36, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
> 
> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> Tegra30 SOCs
> 
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> ---
>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> 
> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> new file mode 100644
> index 0000000..9ee4a66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> @@ -0,0 +1,73 @@
> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> +
> +The NOR controller supports a number of memory types, including synchronous NOR,
> +asynchronous NOR, and other flash memories with similar interfaces, such as
> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> +CAN chips, Wi-Fi chips etc.

Nit-pick ... the Tegra documentation refers to this controller as the
GMI (general memory interface) or SNOR (sync-NOR) controller because it
is not just limited to NOR as you mentioned. I see references to GMI in
the Tegra pinctrl driver and so may be we should use this name.

> +
> +The actual devices are instantiated from the child nodes of a NOR node.
> +
> +Required properties:
> +
> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"

I see at least one difference at the register level between Tegra20 and
Tegra30 and so I think this should be something like ...

 - compatible : Should contain one of the following:
	For Tegra20 must contain "nvidia,tegra20-gmi".
 	For Tegra30 must contain "nvidia,tegra30-gmi".

> + - reg: Should contain NOR controller registers location and length.
> + - clocks: Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> + - resets : Must contain an entry for each entry in reset-names.
> +   See ../reset/reset.txt for details.
> + - reset-names : Must include the following entries:
> +  - nor
> + - #address-cells: Must be set to 2 to allow memory address translation
> + - #size-cells:	Must be set to 1 to allow CS address passing
> + - ranges: Must be set up to reflect the memory layout with four integer
> + 		values for each chip-select line in use.
> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.

There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
that this should be nvidia,snor-config to be explicit. It might be nice
to also add a "nvidia,mio-config" while you are at it as well, however,
that could always be done later. If you do, then the
"nvidia,snor-config" becomes optional depending on whether you are using
the SNOR or MIO address space.

Thierry, Stephen, do prefer all the fields on the config registers are
broken out? There are quite a few but I am not sure what we typically
recommend here?

> +
> +Note that the NOR controller does not have any internal chip-select address
> +decoding and if you want to access multiple devices external chip-select
> +decoding must be provided.

Although it is true, you do have the MIO address space and so you could
support two devices via the SNOR address space and MIO address space
(assuming that the MIO can be used for the 2nd device).

Furthermore, if you do have external logic to support multiple devices
this would assume that the devices use the same timing and so are
probably the same type. It also assumes both can fit in the 256MB
address range. May be worth mentioning.

The GMI does have 8 chip selects and I believe the purpose of these is
to allow you to address more than the 256MB range. However, I believe to
do this it require software intervention to change the current CS that
is in use.

I wonder if it is worth mentioning that the chip-select specified in the
"nvidia,config" prop should match that in the "ranges" prop unless you
have some external decoding logic to provide an external chip-select.
Which raises a question, what does the chip-select in the ranges
actually represent? I am not sure if there is a common practice here for
device tree when boards have external logic to provide additional
chip-selects. I am sure this is quite common.

> +Optional properties:
> +
> + - nvidia,cs-timing: The timing array represents the SNOR_TIMING0_0 and
> +   SNOR_TIMING1_0 registers for the NOR controller. If unset reset-values will
> +   be used. See reference documentation for detailed description of the timing
> +   registers.
> +
> +Example with two SJA1000 CAN controllers connected to the NOR bus:
> +
> +	nor@70009000 {
> +		status = "okay";
> +		compatible = "nvidia,tegra20-nor", "nvidia,tegra30-nor";
> +		reg = <0x70009000 0x1000>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		clocks = <&tegra_car TEGRA30_CLK_NOR>;
> +		resets = < &tegra_car 42>;
> +		reset-names = "nor";
> +		ranges = <
> +			0 0 0x48000000 0x00000100
> +			1 0 0x48040000 0x00000100
> +		>;

The "nvidia,config" appears to be missing here.

Cheers
Jon

On 20/07/16 20:28, Mirza Krak wrote:
> 2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
>> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>
>>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>>> Tegra30 SOCs
>>>
>>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>>> ---
>>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>>>  1 file changed, 73 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>> new file mode 100644
>>> index 0000000..9ee4a66
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>> @@ -0,0 +1,73 @@
>>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
>>> +
>>> +The NOR controller supports a number of memory types, including synchronous NOR,
>>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>>> +CAN chips, Wi-Fi chips etc.
>>> +
>>> +The actual devices are instantiated from the child nodes of a NOR node.
>>> +
>>> +Required properties:
>>> +
>>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>>> + - reg: Should contain NOR controller registers location and length.
>>> + - clocks: Must contain one entry, for the module clock.
>>> +   See ../clocks/clock-bindings.txt for details.
>>> + - resets : Must contain an entry for each entry in reset-names.
>>> +   See ../reset/reset.txt for details.
>>> + - reset-names : Must include the following entries:
>>> +  - nor
>>> + - #address-cells: Must be set to 2 to allow memory address translation
>>> + - #size-cells:      Must be set to 1 to allow CS address passing
>>> + - ranges: Must be set up to reflect the memory layout with four integer
>>> +             values for each chip-select line in use.
>>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>>> +
>>> +Note that the NOR controller does not have any internal chip-select address
>>> +decoding and if you want to access multiple devices external chip-select
>>> +decoding must be provided.
>>
>> Then what are the 2 chip selects in ranges?
>>
>> Rob
> 
> Those two chip selects are actually a representation of a external
> decoding logic based on what we use on our board. Even though it the
> NOR controller only supports one single chip select I wanted to give
> an example on how one could create more chip-selects with an external
> logic and what it would look like in the device tree representation.

Technically, the GMI/SNOR controller supports 8 chip-selects, however,
unlike some devices, it appears that software has to select the active
chip-select. Although this sounds odd, I believe that the idea is that
in order to support devices greater than 256MB (external address space
for available NOR/async devices) you can use the chip-selects to page
through memory greater than this 256MB range. At least that it my
(limited) understanding!

Cheers
Jon

2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>> +
>> +The NOR controller supports a number of memory types, including synchronous NOR,
>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>> +CAN chips, Wi-Fi chips etc.
>
> Nit-pick ... the Tegra documentation refers to this controller as the
> GMI (general memory interface) or SNOR (sync-NOR) controller because it
> is not just limited to NOR as you mentioned. I see references to GMI in
> the Tegra pinctrl driver and so may be we should use this name.

ACK.


>> +Required properties:
>> +
>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>
> I see at least one difference at the register level between Tegra20 and
> Tegra30 and so I think this should be something like ...
>
>  - compatible : Should contain one of the following:
>         For Tegra20 must contain "nvidia,tegra20-gmi".
>         For Tegra30 must contain "nvidia,tegra30-gmi".

ACK. Just curious, which register was it? I only checked that they
have the same count of registers.

>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>
> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
> that this should be nvidia,snor-config to be explicit. It might be nice
> to also add a "nvidia,mio-config" while you are at it as well, however,
> that could always be done later. If you do, then the
> "nvidia,snor-config" becomes optional depending on whether you are using
> the SNOR or MIO address space.

ACK the nvidia,snor-config part, will though wait for further comments
regarding what to do with the config registers, break-out or keep it
is a one property / register.

Regarding mio-config, not sure about if I would like to include that
part in this stage. If you feel strongly about this we can do it. If
it only comes to down to replicate the same configurations that we do
for SNOR to MIO then I do not see much of a problem, but would like
SNOR to be accepted and would not like the MIO part to halt this. But
then again this up to you guys.

>
>> +
>> +Note that the NOR controller does not have any internal chip-select address
>> +decoding and if you want to access multiple devices external chip-select
>> +decoding must be provided.
>
> Although it is true, you do have the MIO address space and so you could
> support two devices via the SNOR address space and MIO address space
> (assuming that the MIO can be used for the 2nd device).

This is true. If we include MIO support above could be added to the bindings.

>
> Furthermore, if you do have external logic to support multiple devices
> this would assume that the devices use the same timing and so are
> probably the same type. It also assumes both can fit in the 256MB
> address range. May be worth mentioning.

ACK.

>
> The GMI does have 8 chip selects and I believe the purpose of these is
> to allow you to address more than the 256MB range. However, I believe to
> do this it require software intervention to change the current CS that
> is in use.

Yes that is true. One has to modify the SNOR_CONFIG register to choose
a different CS pin.

>
> I wonder if it is worth mentioning that the chip-select specified in the
> "nvidia,config" prop should match that in the "ranges" prop unless you
> have some external decoding logic to provide an external chip-select.
> Which raises a question, what does the chip-select in the ranges
> actually represent? I am not sure if there is a common practice here for
> device tree when boards have external logic to provide additional
> chip-selects. I am sure this is quite common.

I do not understand why CS pin setting in nvidia,config need to match
the "ranges" prop? Other then maybe cosmetics.

If we do not have any external decoding logic to create more
chip-selects we only have ONE chip-select, and that one should always
be indexed as 0? Regardless of which CS pin is used. Because
ultimately what we configure in SNOR_CONFIG is which PIN(function) to
use as chip-select. The address space remains the same.

>> +Example with two SJA1000 CAN controllers connected to the NOR bus:
>> +
>> +     nor@70009000 {
>> +             status = "okay";
>> +             compatible = "nvidia,tegra20-nor", "nvidia,tegra30-nor";
>> +             reg = <0x70009000 0x1000>;
>> +             #address-cells = <2>;
>> +             #size-cells = <1>;
>> +             clocks = <&tegra_car TEGRA30_CLK_NOR>;
>> +             resets = < &tegra_car 42>;
>> +             reset-names = "nor";
>> +             ranges = <
>> +                     0 0 0x48000000 0x00000100
>> +                     1 0 0x48040000 0x00000100
>> +             >;
>
> The "nvidia,config" appears to be missing here.

Indeed it is. ACK.

Thank you Jonanthan for your feedback.

Best Regards,
Mirza
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On 21/07/16 21:10, Mirza Krak wrote:
> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>> +
>>> +The NOR controller supports a number of memory types, including synchronous NOR,
>>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>>> +CAN chips, Wi-Fi chips etc.
>>
>> Nit-pick ... the Tegra documentation refers to this controller as the
>> GMI (general memory interface) or SNOR (sync-NOR) controller because it
>> is not just limited to NOR as you mentioned. I see references to GMI in
>> the Tegra pinctrl driver and so may be we should use this name.
> 
> ACK.
> 
> 
>>> +Required properties:
>>> +
>>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>>
>> I see at least one difference at the register level between Tegra20 and
>> Tegra30 and so I think this should be something like ...
>>
>>  - compatible : Should contain one of the following:
>>         For Tegra20 must contain "nvidia,tegra20-gmi".
>>         For Tegra30 must contain "nvidia,tegra30-gmi".
> 
> ACK. Just curious, which register was it? I only checked that they
> have the same count of registers.

Register counts are the same, but the SNOR_CONFIG_0 is not identical. I
believe only Tegra30 defines bit 14.

>>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>>
>> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
>> that this should be nvidia,snor-config to be explicit. It might be nice
>> to also add a "nvidia,mio-config" while you are at it as well, however,
>> that could always be done later. If you do, then the
>> "nvidia,snor-config" becomes optional depending on whether you are using
>> the SNOR or MIO address space.
> 
> ACK the nvidia,snor-config part, will though wait for further comments
> regarding what to do with the config registers, break-out or keep it
> is a one property / register.
> 
> Regarding mio-config, not sure about if I would like to include that
> part in this stage. If you feel strongly about this we can do it. If
> it only comes to down to replicate the same configurations that we do
> for SNOR to MIO then I do not see much of a problem, but would like
> SNOR to be accepted and would not like the MIO part to halt this. But
> then again this up to you guys.
> 
>>
>>> +
>>> +Note that the NOR controller does not have any internal chip-select address
>>> +decoding and if you want to access multiple devices external chip-select
>>> +decoding must be provided.
>>
>> Although it is true, you do have the MIO address space and so you could
>> support two devices via the SNOR address space and MIO address space
>> (assuming that the MIO can be used for the 2nd device).
> 
> This is true. If we include MIO support above could be added to the bindings.
> 
>>
>> Furthermore, if you do have external logic to support multiple devices
>> this would assume that the devices use the same timing and so are
>> probably the same type. It also assumes both can fit in the 256MB
>> address range. May be worth mentioning.
> 
> ACK.
> 
>>
>> The GMI does have 8 chip selects and I believe the purpose of these is
>> to allow you to address more than the 256MB range. However, I believe to
>> do this it require software intervention to change the current CS that
>> is in use.
> 
> Yes that is true. One has to modify the SNOR_CONFIG register to choose
> a different CS pin.
> 
>>
>> I wonder if it is worth mentioning that the chip-select specified in the
>> "nvidia,config" prop should match that in the "ranges" prop unless you
>> have some external decoding logic to provide an external chip-select.
>> Which raises a question, what does the chip-select in the ranges
>> actually represent? I am not sure if there is a common practice here for
>> device tree when boards have external logic to provide additional
>> chip-selects. I am sure this is quite common.
> 
> I do not understand why CS pin setting in nvidia,config need to match
> the "ranges" prop? Other then maybe cosmetics.

Yes it would be cosmetic. That said, I even wonder if CS needs to be
exposed at all given that they all map to the same CPU address space.
Couldn't your binding for the CAN devices be as follows?

nor@70009000 {
	...

	can@48000000 {
		...
	};

	can@48040000 {
		...
	};
};

Problem is if you did have devices on different chip-selects then how
would these be handled? They could not point to the same physical
address. I am not sure if there is a way to do that in DT?

Cheers
Jon

2016-07-22 11:32 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>
> On 21/07/16 21:10, Mirza Krak wrote:
>> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>>
>>> I wonder if it is worth mentioning that the chip-select specified in the
>>> "nvidia,config" prop should match that in the "ranges" prop unless you
>>> have some external decoding logic to provide an external chip-select.
>>> Which raises a question, what does the chip-select in the ranges
>>> actually represent? I am not sure if there is a common practice here for
>>> device tree when boards have external logic to provide additional
>>> chip-selects. I am sure this is quite common.
>>
>> I do not understand why CS pin setting in nvidia,config need to match
>> the "ranges" prop? Other then maybe cosmetics.
>
> Yes it would be cosmetic. That said, I even wonder if CS needs to be
> exposed at all given that they all map to the same CPU address space.
> Couldn't your binding for the CAN devices be as follows?
>
> nor@70009000 {
>         ...
>
>         can@48000000 {
>                 ...
>         };
>
>         can@48040000 {
>                 ...
>         };
> };

This has also crossed my mind, maybe just get rid of the "ranges" prop
and do like you have above. But then again I do not know what is
preferred so I went with "ranges" prop initially.


>
> Problem is if you did have devices on different chip-selects then how
> would these be handled? They could not point to the same physical
> address. I am not sure if there is a way to do that in DT?

Having trouble following your though here. We do not have "different"
chip-selects?

Best Regards
Mirza
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On 22/07/16 20:07, Mirza Krak wrote:
> 2016-07-22 11:32 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>
>> On 21/07/16 21:10, Mirza Krak wrote:
>>> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>>>
>>>> I wonder if it is worth mentioning that the chip-select specified in the
>>>> "nvidia,config" prop should match that in the "ranges" prop unless you
>>>> have some external decoding logic to provide an external chip-select.
>>>> Which raises a question, what does the chip-select in the ranges
>>>> actually represent? I am not sure if there is a common practice here for
>>>> device tree when boards have external logic to provide additional
>>>> chip-selects. I am sure this is quite common.
>>>
>>> I do not understand why CS pin setting in nvidia,config need to match
>>> the "ranges" prop? Other then maybe cosmetics.
>>
>> Yes it would be cosmetic. That said, I even wonder if CS needs to be
>> exposed at all given that they all map to the same CPU address space.
>> Couldn't your binding for the CAN devices be as follows?
>>
>> nor@70009000 {
>>         ...
>>
>>         can@48000000 {
>>                 ...
>>         };
>>
>>         can@48040000 {
>>                 ...
>>         };
>> };
> 
> This has also crossed my mind, maybe just get rid of the "ranges" prop
> and do like you have above. But then again I do not know what is
> preferred so I went with "ranges" prop initially.
> 
> 
>>
>> Problem is if you did have devices on different chip-selects then how
>> would these be handled? They could not point to the same physical
>> address. I am not sure if there is a way to do that in DT?
> 
> Having trouble following your though here. We do not have "different"
> chip-selects?

I meant that the device has multiple chip-selects and so I was not sure
the best way to handle this for the GMI.

Jon

On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
> 
> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> Tegra30 SOCs
> 
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> ---
>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>  1 file changed, 73 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> 
> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> new file mode 100644
> index 0000000..9ee4a66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> @@ -0,0 +1,73 @@
> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> +
> +The NOR controller supports a number of memory types, including synchronous NOR,
> +asynchronous NOR, and other flash memories with similar interfaces, such as
> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> +CAN chips, Wi-Fi chips etc.
> +
> +The actual devices are instantiated from the child nodes of a NOR node.
> +
> +Required properties:
> +
> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> + - reg: Should contain NOR controller registers location and length.
> + - clocks: Must contain one entry, for the module clock.
> +   See ../clocks/clock-bindings.txt for details.
> + - resets : Must contain an entry for each entry in reset-names.
> +   See ../reset/reset.txt for details.
> + - reset-names : Must include the following entries:
> +  - nor
> + - #address-cells: Must be set to 2 to allow memory address translation
> + - #size-cells:	Must be set to 1 to allow CS address passing
> + - ranges: Must be set up to reflect the memory layout with four integer
> + 		values for each chip-select line in use.
> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.

I'd prefer if this was split out into separate properties. It's somewhat
friendlier in my opinion to let people know what each of the settings is
along with any units and such, rather than point them at the TRM, which
they may or may not have access to.

Or which not be available anymore.

> +
> +Note that the NOR controller does not have any internal chip-select address
> +decoding and if you want to access multiple devices external chip-select
> +decoding must be provided.
> +
> +Optional properties:
> +
> + - nvidia,cs-timing: The timing array represents the SNOR_TIMING0_0 and
> +   SNOR_TIMING1_0 registers for the NOR controller. If unset reset-values will
> +   be used. See reference documentation for detailed description of the timing
> +   registers.

Are the reset values sensible? Are they reasonable defaults for a class
of use-cases? I'm thinking that if they aren't we might as well make it
a required property.

Also, I'd prefer if this was split out into individual fields for the
same reasons as the SNOR_CONFIG_0 register property.

> +
> +Example with two SJA1000 CAN controllers connected to the NOR bus:
> +
> +	nor@70009000 {
> +		status = "okay";
> +		compatible = "nvidia,tegra20-nor", "nvidia,tegra30-nor";
> +		reg = <0x70009000 0x1000>;
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		clocks = <&tegra_car TEGRA30_CLK_NOR>;
> +		resets = < &tegra_car 42>;

No space between < and &, please.

> +		reset-names = "nor";
> +		ranges = <
> +			0 0 0x48000000 0x00000100
> +			1 0 0x48040000 0x00000100
> +		>;
> +
> +		can@0,0 {
> +			compatible = "nxp,sja1000";
> +			reg = <0 0 0x100>;
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_GPIO(B, 5) IRQ_TYPE_EDGE_RISING>;
> +			nxp,external-clock-frequency = <24000000>;
> +			nxp,tx-output-config = <0x16>;
> +			nxp,clock-out-frequency = <24000000>;
> +			reg-io-width = <2>;
> +		};
> +
> +

There's an extra blank line here.

> +		can@1,0 {
> +			compatible = "nxp,sja1000";
> +			reg = <1 0 0x100>;
> +			interrupt-parent = <&gpio>;
> +			interrupts = <TEGRA_GPIO(A, 6) IRQ_TYPE_EDGE_RISING>;
> +			nxp,external-clock-frequency = <24000000>;
> +			nxp,tx-output-config = <0x16>;
> +			reg-io-width = <2>;
> +	};

I'm somewhat confused about how this hardware works. My understanding
was that each chip gets mapped to the whole range of the NOR address
range (0x48000000 - 0x4fffffff on Tegra30).

The above suggests that one of the CAN controllers gets mapped to an
address 0x48000000 and the other gets mapped to 0x48040000. But why do
we even need a chip-select at all in that case? If both chips don't use
any overlapping memory region, what good does the chip-select do?

Also, it seems to me that you'd have to program the SNOR_CONFIG_0
register in order to select a specific chip, but I don't see anything in
the driver access that register after the initial write of the register.

I would've expected this to require some sort of infrastructure to allow
devices connected to the GMI controller to acquire the bus via some API
to select their chip.

Thierry

On Thu, Jul 21, 2016 at 11:26:09AM +0100, Jon Hunter wrote:
> 
> On 20/07/16 20:28, Mirza Krak wrote:
> > 2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
> >> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
> >>> From: Mirza Krak <mirza.krak@gmail.com>
> >>>
> >>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> >>> Tegra30 SOCs
> >>>
> >>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> >>> ---
> >>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
> >>>  1 file changed, 73 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>> new file mode 100644
> >>> index 0000000..9ee4a66
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>> @@ -0,0 +1,73 @@
> >>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> >>> +
> >>> +The NOR controller supports a number of memory types, including synchronous NOR,
> >>> +asynchronous NOR, and other flash memories with similar interfaces, such as
> >>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> >>> +CAN chips, Wi-Fi chips etc.
> >>> +
> >>> +The actual devices are instantiated from the child nodes of a NOR node.
> >>> +
> >>> +Required properties:
> >>> +
> >>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> >>> + - reg: Should contain NOR controller registers location and length.
> >>> + - clocks: Must contain one entry, for the module clock.
> >>> +   See ../clocks/clock-bindings.txt for details.
> >>> + - resets : Must contain an entry for each entry in reset-names.
> >>> +   See ../reset/reset.txt for details.
> >>> + - reset-names : Must include the following entries:
> >>> +  - nor
> >>> + - #address-cells: Must be set to 2 to allow memory address translation
> >>> + - #size-cells:      Must be set to 1 to allow CS address passing
> >>> + - ranges: Must be set up to reflect the memory layout with four integer
> >>> +             values for each chip-select line in use.
> >>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> >>> +
> >>> +Note that the NOR controller does not have any internal chip-select address
> >>> +decoding and if you want to access multiple devices external chip-select
> >>> +decoding must be provided.
> >>
> >> Then what are the 2 chip selects in ranges?
> >>
> >> Rob
> > 
> > Those two chip selects are actually a representation of a external
> > decoding logic based on what we use on our board. Even though it the
> > NOR controller only supports one single chip select I wanted to give
> > an example on how one could create more chip-selects with an external
> > logic and what it would look like in the device tree representation.
> 
> Technically, the GMI/SNOR controller supports 8 chip-selects, however,
> unlike some devices, it appears that software has to select the active
> chip-select. Although this sounds odd, I believe that the idea is that
> in order to support devices greater than 256MB (external address space
> for available NOR/async devices) you can use the chip-selects to page
> through memory greater than this 256MB range. At least that it my
> (limited) understanding!

Actually I had assumed that software would at some point need to select
the active chip to switch between multiple connected chips. I suppose it
could be possible to have multiple chips share the same chip-select and
decode the address lines to determine whether they're being accessed or
not.

What I don't understand, and it's further complicated by the fact that
external chip-selects are being used, is how does the controller get
told what chip to select? It seems to me like it would always access the
same chips because the SNOR_CONFIG_0 register is only ever written on
->probe().

For external chip selects, how do they tie in with all this? Who gets to
implement this logic? Wouldn't we need to abstract this away somehow so
that we can support whatever board designers will come up with?

Thierry

On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
> 
> On 19/07/16 14:36, Mirza Krak wrote:
> > From: Mirza Krak <mirza.krak@gmail.com>
> > 
> > Document the devicetree bindings for NOR bus driver found on Tegra20 and
> > Tegra30 SOCs
> > 
> > Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> > ---
> >  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
> >  1 file changed, 73 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> > new file mode 100644
> > index 0000000..9ee4a66
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> > @@ -0,0 +1,73 @@
> > +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> > +
> > +The NOR controller supports a number of memory types, including synchronous NOR,
> > +asynchronous NOR, and other flash memories with similar interfaces, such as
> > +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> > +CAN chips, Wi-Fi chips etc.
> 
> Nit-pick ... the Tegra documentation refers to this controller as the
> GMI (general memory interface) or SNOR (sync-NOR) controller because it
> is not just limited to NOR as you mentioned. I see references to GMI in
> the Tegra pinctrl driver and so may be we should use this name.
> 
> > +
> > +The actual devices are instantiated from the child nodes of a NOR node.
> > +
> > +Required properties:
> > +
> > + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> 
> I see at least one difference at the register level between Tegra20 and
> Tegra30 and so I think this should be something like ...
> 
>  - compatible : Should contain one of the following:
> 	For Tegra20 must contain "nvidia,tegra20-gmi".
>  	For Tegra30 must contain "nvidia,tegra30-gmi".
> 
> > + - reg: Should contain NOR controller registers location and length.
> > + - clocks: Must contain one entry, for the module clock.
> > +   See ../clocks/clock-bindings.txt for details.
> > + - resets : Must contain an entry for each entry in reset-names.
> > +   See ../reset/reset.txt for details.
> > + - reset-names : Must include the following entries:
> > +  - nor
> > + - #address-cells: Must be set to 2 to allow memory address translation
> > + - #size-cells:	Must be set to 1 to allow CS address passing
> > + - ranges: Must be set up to reflect the memory layout with four integer
> > + 		values for each chip-select line in use.
> > + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> 
> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
> that this should be nvidia,snor-config to be explicit. It might be nice
> to also add a "nvidia,mio-config" while you are at it as well, however,
> that could always be done later. If you do, then the
> "nvidia,snor-config" becomes optional depending on whether you are using
> the SNOR or MIO address space.
> 
> Thierry, Stephen, do prefer all the fields on the config registers are
> broken out? There are quite a few but I am not sure what we typically
> recommend here?

As I said elsewhere, I prefer breaking the fields out into separate
properties because that makes it a lot easier to write the DT. Rather
than having to go and manually assemble 32-bit values for this register
and the timing registers, it must be a lot easier to look at datasheets
and copy the values into the corresponding DT properties.

> > +Note that the NOR controller does not have any internal chip-select address
> > +decoding and if you want to access multiple devices external chip-select
> > +decoding must be provided.
> 
> Although it is true, you do have the MIO address space and so you could
> support two devices via the SNOR address space and MIO address space
> (assuming that the MIO can be used for the 2nd device).

Now I'm even more confused. If the GMI controller itself can't select a
chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
that not select a specific chip?

> Furthermore, if you do have external logic to support multiple devices
> this would assume that the devices use the same timing and so are
> probably the same type. It also assumes both can fit in the 256MB
> address range. May be worth mentioning.

Similarly if you switch between different devices, wouldn't you have to
reprogram the timing registers if they are different?

The way I remember this kind of interface to work (it's been a long time
since I used one) is that in order to operate on a chip you need to
acquire the bus first. Typically that would be an API exposed by the bus
driver or some framework that the bus driver registers with. That API
arbitrates between multiple devices on the bus and makes sure that the
proper chip select is asserted and timing is programmed when you're
granted access. A driver that has acquired the bus can then perform what
operations they need and release the bus when done.

SPI uses a mechanism like this, for example.

Thierry

On Thu, Jul 21, 2016 at 10:10:49PM +0200, Mirza Krak wrote:
> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
> >> +
> >> +The NOR controller supports a number of memory types, including synchronous NOR,
> >> +asynchronous NOR, and other flash memories with similar interfaces, such as
> >> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> >> +CAN chips, Wi-Fi chips etc.
> >
> > Nit-pick ... the Tegra documentation refers to this controller as the
> > GMI (general memory interface) or SNOR (sync-NOR) controller because it
> > is not just limited to NOR as you mentioned. I see references to GMI in
> > the Tegra pinctrl driver and so may be we should use this name.
> 
> ACK.
> 
> 
> >> +Required properties:
> >> +
> >> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> >
> > I see at least one difference at the register level between Tegra20 and
> > Tegra30 and so I think this should be something like ...
> >
> >  - compatible : Should contain one of the following:
> >         For Tegra20 must contain "nvidia,tegra20-gmi".
> >         For Tegra30 must contain "nvidia,tegra30-gmi".
> 
> ACK. Just curious, which register was it? I only checked that they
> have the same count of registers.
> 
> >> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> >
> > There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
> > that this should be nvidia,snor-config to be explicit. It might be nice
> > to also add a "nvidia,mio-config" while you are at it as well, however,
> > that could always be done later. If you do, then the
> > "nvidia,snor-config" becomes optional depending on whether you are using
> > the SNOR or MIO address space.
> 
> ACK the nvidia,snor-config part, will though wait for further comments
> regarding what to do with the config registers, break-out or keep it
> is a one property / register.
> 
> Regarding mio-config, not sure about if I would like to include that
> part in this stage. If you feel strongly about this we can do it. If
> it only comes to down to replicate the same configurations that we do
> for SNOR to MIO then I do not see much of a problem, but would like
> SNOR to be accepted and would not like the MIO part to halt this. But
> then again this up to you guys.

What's the difference between SNOR and MIO? Sorry if I'm being dense but
a quick look around the internet didn't yield anything related. I'd be
happy to read up if somebody can provide a link.

> > I wonder if it is worth mentioning that the chip-select specified in the
> > "nvidia,config" prop should match that in the "ranges" prop unless you
> > have some external decoding logic to provide an external chip-select.
> > Which raises a question, what does the chip-select in the ranges
> > actually represent? I am not sure if there is a common practice here for
> > device tree when boards have external logic to provide additional
> > chip-selects. I am sure this is quite common.
> 
> I do not understand why CS pin setting in nvidia,config need to match
> the "ranges" prop? Other then maybe cosmetics.
> 
> If we do not have any external decoding logic to create more
> chip-selects we only have ONE chip-select, and that one should always
> be indexed as 0? Regardless of which CS pin is used. Because
> ultimately what we configure in SNOR_CONFIG is which PIN(function) to
> use as chip-select. The address space remains the same.

Is that really so? Looking at the list of pins there are 8 CS outputs
from the GMI controller. That and the presence of the SNOR_SEL field in
the SNOR_CONFIG_0 register indicate to me that you can use software to
assert any of the CS outputs (though only one at the same time, which
makes sense since you want to avoid writing to multiple chips at once).

Of course the documentation is to blame here, it doesn't go into any
detail at all about how to use the GMI controller.

Thierry

On 25/07/16 13:10, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Thu, Jul 21, 2016 at 10:10:49PM +0200, Mirza Krak wrote:
>> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
>>>> +
>>>> +The NOR controller supports a number of memory types, including synchronous NOR,
>>>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>>>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>>>> +CAN chips, Wi-Fi chips etc.
>>>
>>> Nit-pick ... the Tegra documentation refers to this controller as the
>>> GMI (general memory interface) or SNOR (sync-NOR) controller because it
>>> is not just limited to NOR as you mentioned. I see references to GMI in
>>> the Tegra pinctrl driver and so may be we should use this name.
>>
>> ACK.
>>
>>
>>>> +Required properties:
>>>> +
>>>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>>>
>>> I see at least one difference at the register level between Tegra20 and
>>> Tegra30 and so I think this should be something like ...
>>>
>>>  - compatible : Should contain one of the following:
>>>         For Tegra20 must contain "nvidia,tegra20-gmi".
>>>         For Tegra30 must contain "nvidia,tegra30-gmi".
>>
>> ACK. Just curious, which register was it? I only checked that they
>> have the same count of registers.
>>
>>>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>>>
>>> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
>>> that this should be nvidia,snor-config to be explicit. It might be nice
>>> to also add a "nvidia,mio-config" while you are at it as well, however,
>>> that could always be done later. If you do, then the
>>> "nvidia,snor-config" becomes optional depending on whether you are using
>>> the SNOR or MIO address space.
>>
>> ACK the nvidia,snor-config part, will though wait for further comments
>> regarding what to do with the config registers, break-out or keep it
>> is a one property / register.
>>
>> Regarding mio-config, not sure about if I would like to include that
>> part in this stage. If you feel strongly about this we can do it. If
>> it only comes to down to replicate the same configurations that we do
>> for SNOR to MIO then I do not see much of a problem, but would like
>> SNOR to be accepted and would not like the MIO part to halt this. But
>> then again this up to you guys.
> 
> What's the difference between SNOR and MIO? Sorry if I'm being dense but
> a quick look around the internet didn't yield anything related. I'd be
> happy to read up if somebody can provide a link.

I am not sure where this term MIO comes from (may be an NVIDIA term),
but from looking at the MIO_CONFIG register, it looks like a basic
16/32-bit interface with configurable read/write strobe timing. Does not
support bursting or address/data multiplexing that the SNOR interface
does. So may be it is used for interfacing to external devices such as
FIFOs, UARTs, I2C expanders, etc.

Cheers
Jon

2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>> Tegra30 SOCs
>>
>> +
>> +Required properties:
>> +
>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>> + - reg: Should contain NOR controller registers location and length.
>> + - clocks: Must contain one entry, for the module clock.
>> +   See ../clocks/clock-bindings.txt for details.
>> + - resets : Must contain an entry for each entry in reset-names.
>> +   See ../reset/reset.txt for details.
>> + - reset-names : Must include the following entries:
>> +  - nor
>> + - #address-cells: Must be set to 2 to allow memory address translation
>> + - #size-cells:      Must be set to 1 to allow CS address passing
>> + - ranges: Must be set up to reflect the memory layout with four integer
>> +             values for each chip-select line in use.
>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>
> I'd prefer if this was split out into separate properties. It's somewhat
> friendlier in my opinion to let people know what each of the settings is
> along with any units and such, rather than point them at the TRM, which
> they may or may not have access to.
>
> Or which not be available anymore.

Will split it out.

>
>> +
>> +Note that the NOR controller does not have any internal chip-select address
>> +decoding and if you want to access multiple devices external chip-select
>> +decoding must be provided.
>> +
>> +Optional properties:
>> +
>> + - nvidia,cs-timing: The timing array represents the SNOR_TIMING0_0 and
>> +   SNOR_TIMING1_0 registers for the NOR controller. If unset reset-values will
>> +   be used. See reference documentation for detailed description of the timing
>> +   registers.
>
> Are the reset values sensible? Are they reasonable defaults for a class
> of use-cases? I'm thinking that if they aren't we might as well make it
> a required property.
>
> Also, I'd prefer if this was split out into individual fields for the
> same reasons as the SNOR_CONFIG_0 register property.

I have tested the default values with two different chip types, and
both have worked without me adjusting any timings. The tested chips
are SJA1000 (CAN) and 16C550 (UART). So I would say that they are
sensible.

Will split it out as well.

>
>> +
>> +Example with two SJA1000 CAN controllers connected to the NOR bus:
>> +
>> +     nor@70009000 {
>> +             status = "okay";
>> +             compatible = "nvidia,tegra20-nor", "nvidia,tegra30-nor";
>> +             reg = <0x70009000 0x1000>;
>> +             #address-cells = <2>;
>> +             #size-cells = <1>;
>> +             clocks = <&tegra_car TEGRA30_CLK_NOR>;
>> +             resets = < &tegra_car 42>;
>
> No space between < and &, please.

ACK.

>
>> +             reset-names = "nor";
>> +             ranges = <
>> +                     0 0 0x48000000 0x00000100
>> +                     1 0 0x48040000 0x00000100
>> +             >;
>> +
>> +             can@0,0 {
>> +                     compatible = "nxp,sja1000";
>> +                     reg = <0 0 0x100>;
>> +                     interrupt-parent = <&gpio>;
>> +                     interrupts = <TEGRA_GPIO(B, 5) IRQ_TYPE_EDGE_RISING>;
>> +                     nxp,external-clock-frequency = <24000000>;
>> +                     nxp,tx-output-config = <0x16>;
>> +                     nxp,clock-out-frequency = <24000000>;
>> +                     reg-io-width = <2>;
>> +             };
>> +
>> +
>
> There's an extra blank line here.

ACK.

>
>> +             can@1,0 {
>> +                     compatible = "nxp,sja1000";
>> +                     reg = <1 0 0x100>;
>> +                     interrupt-parent = <&gpio>;
>> +                     interrupts = <TEGRA_GPIO(A, 6) IRQ_TYPE_EDGE_RISING>;
>> +                     nxp,external-clock-frequency = <24000000>;
>> +                     nxp,tx-output-config = <0x16>;
>> +                     reg-io-width = <2>;
>> +     };
>
> I'm somewhat confused about how this hardware works. My understanding
> was that each chip gets mapped to the whole range of the NOR address
> range (0x48000000 - 0x4fffffff on Tegra30).

I can understand the confusion.

>
> The above suggests that one of the CAN controllers gets mapped to an
> address 0x48000000 and the other gets mapped to 0x48040000. But why do
> we even need a chip-select at all in that case? If both chips don't use
> any overlapping memory region, what good does the chip-select do?

If we take a look on similar controllers found on others SOCs they
usually define an address range / chip-select.

Example (weim):
ranges = <
0 0 0x10000000 0x02000000
1 0 0x12000000 0x01000000
2 0 0x13000000 0x01000000
3 0 0x14000000 0x01000000
4 0 0x15000000 0x01000000
5 0 0x16000000 0x01000000
>;

Which means that you all ready have an address mapped to PIN function.

But Tegra GMI controller is a first for me, where you do not have this
kind of setup in hardware. Usually you also have a timing register /
chip-select so that you can connect different chip types.

The lack of hardware support do decode an address to a chip-select PIN
function, we have implemented this our self externally.

We actually have 6 different chips connected to the GMI bus and the
"ranges" would be:
  ranges = <
   0 0 0x48000000 0x00000100
   1 0 0x48040000 0x00000100
   2 0 0x48080000 0x00000100
   3 0 0x480A0000 0x00000100
   4 0 0x480C0000 0x00000100
   5 0 0x480E0000 0x00000100
  >;

And this not nothing complicated, small number of AND gates and that is it.

The chip-select signal is necessary for the access characteristics, so
we need to translate an address to an chip-select so that the chip
knows the host CPU wants to talk to it.

Do not know if I made anything more clear here :).

>
> Also, it seems to me that you'd have to program the SNOR_CONFIG_0
> register in order to select a specific chip, but I don't see anything in
> the driver access that register after the initial write of the register.

This is only setup at probe.

>
> I would've expected this to require some sort of infrastructure to allow
> devices connected to the GMI controller to acquire the bus via some API
> to select their chip.

Yes, ultimately you would need some sort of infrastructure to allow
devices to acquire the GMI bus if you want to solve this in software.
But at the moment I do not see such an infrastructure in place, and is
it feasible to add one specifically for the GMI controller? If one
such infrastructure was in place we would need to modify all the
drivers that want to use to include Tegra specific infrastructure to
access the GMI bus?

Since my knowledge is limited it hard for me to comment on this, maybe
there is a simple way of doing this?


Best Regards,
Mirza
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2016-07-25 13:36 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Thu, Jul 21, 2016 at 11:26:09AM +0100, Jon Hunter wrote:
>>
>> On 20/07/16 20:28, Mirza Krak wrote:
>> > 2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
>> >> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
>> >>> From: Mirza Krak <mirza.krak@gmail.com>
>> >>>
>> >>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>> >>> Tegra30 SOCs
>> >>>
>> >>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>> >>> ---
>> >>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>> >>>  1 file changed, 73 insertions(+)
>> >>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >>>
>> >>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >>> new file mode 100644
>> >>> index 0000000..9ee4a66
>> >>> --- /dev/null
>> >>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >>> @@ -0,0 +1,73 @@
>> >>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
>> >>> +
>> >>> +The NOR controller supports a number of memory types, including synchronous NOR,
>> >>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>> >>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>> >>> +CAN chips, Wi-Fi chips etc.
>> >>> +
>> >>> +The actual devices are instantiated from the child nodes of a NOR node.
>> >>> +
>> >>> +Required properties:
>> >>> +
>> >>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>> >>> + - reg: Should contain NOR controller registers location and length.
>> >>> + - clocks: Must contain one entry, for the module clock.
>> >>> +   See ../clocks/clock-bindings.txt for details.
>> >>> + - resets : Must contain an entry for each entry in reset-names.
>> >>> +   See ../reset/reset.txt for details.
>> >>> + - reset-names : Must include the following entries:
>> >>> +  - nor
>> >>> + - #address-cells: Must be set to 2 to allow memory address translation
>> >>> + - #size-cells:      Must be set to 1 to allow CS address passing
>> >>> + - ranges: Must be set up to reflect the memory layout with four integer
>> >>> +             values for each chip-select line in use.
>> >>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>> >>> +
>> >>> +Note that the NOR controller does not have any internal chip-select address
>> >>> +decoding and if you want to access multiple devices external chip-select
>> >>> +decoding must be provided.
>> >>
>> >> Then what are the 2 chip selects in ranges?
>> >>
>> >> Rob
>> >
>> > Those two chip selects are actually a representation of a external
>> > decoding logic based on what we use on our board. Even though it the
>> > NOR controller only supports one single chip select I wanted to give
>> > an example on how one could create more chip-selects with an external
>> > logic and what it would look like in the device tree representation.
>>
>> Technically, the GMI/SNOR controller supports 8 chip-selects, however,
>> unlike some devices, it appears that software has to select the active
>> chip-select. Although this sounds odd, I believe that the idea is that
>> in order to support devices greater than 256MB (external address space
>> for available NOR/async devices) you can use the chip-selects to page
>> through memory greater than this 256MB range. At least that it my
>> (limited) understanding!
>
> Actually I had assumed that software would at some point need to select
> the active chip to switch between multiple connected chips. I suppose it
> could be possible to have multiple chips share the same chip-select and
> decode the address lines to determine whether they're being accessed or
> not.
>
> What I don't understand, and it's further complicated by the fact that
> external chip-selects are being used, is how does the controller get
> told what chip to select? It seems to me like it would always access the
> same chips because the SNOR_CONFIG_0 register is only ever written on
> ->probe().
>
> For external chip selects, how do they tie in with all this? Who gets to
> implement this logic? Wouldn't we need to abstract this away somehow so
> that we can support whatever board designers will come up with?
>
> Thierry

You answered it your self :).

>I suppose it
> could be possible to have multiple chips share the same chip-select and
> decode the address lines to determine whether they're being accessed or
> not.

That is what we do and is what I refer to as external chip-selects.


Best Regards,
Mirza
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On Mon, Jul 25, 2016 at 03:20:44PM +0200, Mirza Krak wrote:
> 2016-07-25 13:36 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> > On Thu, Jul 21, 2016 at 11:26:09AM +0100, Jon Hunter wrote:
> >>
> >> On 20/07/16 20:28, Mirza Krak wrote:
> >> > 2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
> >> >> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
> >> >>> From: Mirza Krak <mirza.krak@gmail.com>
> >> >>>
> >> >>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> >> >>> Tegra30 SOCs
> >> >>>
> >> >>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> >> >>> ---
> >> >>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
> >> >>>  1 file changed, 73 insertions(+)
> >> >>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >> >>>
> >> >>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >> >>> new file mode 100644
> >> >>> index 0000000..9ee4a66
> >> >>> --- /dev/null
> >> >>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >> >>> @@ -0,0 +1,73 @@
> >> >>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> >> >>> +
> >> >>> +The NOR controller supports a number of memory types, including synchronous NOR,
> >> >>> +asynchronous NOR, and other flash memories with similar interfaces, such as
> >> >>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> >> >>> +CAN chips, Wi-Fi chips etc.
> >> >>> +
> >> >>> +The actual devices are instantiated from the child nodes of a NOR node.
> >> >>> +
> >> >>> +Required properties:
> >> >>> +
> >> >>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> >> >>> + - reg: Should contain NOR controller registers location and length.
> >> >>> + - clocks: Must contain one entry, for the module clock.
> >> >>> +   See ../clocks/clock-bindings.txt for details.
> >> >>> + - resets : Must contain an entry for each entry in reset-names.
> >> >>> +   See ../reset/reset.txt for details.
> >> >>> + - reset-names : Must include the following entries:
> >> >>> +  - nor
> >> >>> + - #address-cells: Must be set to 2 to allow memory address translation
> >> >>> + - #size-cells:      Must be set to 1 to allow CS address passing
> >> >>> + - ranges: Must be set up to reflect the memory layout with four integer
> >> >>> +             values for each chip-select line in use.
> >> >>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> >> >>> +
> >> >>> +Note that the NOR controller does not have any internal chip-select address
> >> >>> +decoding and if you want to access multiple devices external chip-select
> >> >>> +decoding must be provided.
> >> >>
> >> >> Then what are the 2 chip selects in ranges?
> >> >>
> >> >> Rob
> >> >
> >> > Those two chip selects are actually a representation of a external
> >> > decoding logic based on what we use on our board. Even though it the
> >> > NOR controller only supports one single chip select I wanted to give
> >> > an example on how one could create more chip-selects with an external
> >> > logic and what it would look like in the device tree representation.
> >>
> >> Technically, the GMI/SNOR controller supports 8 chip-selects, however,
> >> unlike some devices, it appears that software has to select the active
> >> chip-select. Although this sounds odd, I believe that the idea is that
> >> in order to support devices greater than 256MB (external address space
> >> for available NOR/async devices) you can use the chip-selects to page
> >> through memory greater than this 256MB range. At least that it my
> >> (limited) understanding!
> >
> > Actually I had assumed that software would at some point need to select
> > the active chip to switch between multiple connected chips. I suppose it
> > could be possible to have multiple chips share the same chip-select and
> > decode the address lines to determine whether they're being accessed or
> > not.
> >
> > What I don't understand, and it's further complicated by the fact that
> > external chip-selects are being used, is how does the controller get
> > told what chip to select? It seems to me like it would always access the
> > same chips because the SNOR_CONFIG_0 register is only ever written on
> > ->probe().
> >
> > For external chip selects, how do they tie in with all this? Who gets to
> > implement this logic? Wouldn't we need to abstract this away somehow so
> > that we can support whatever board designers will come up with?
> >
> > Thierry
> 
> You answered it your self :).
> 
> >I suppose it
> > could be possible to have multiple chips share the same chip-select and
> > decode the address lines to determine whether they're being accessed or
> > not.
> 
> That is what we do and is what I refer to as external chip-selects.

Okay, so there aren't actually chips or pins that serve as external chip
selects, but rather the GMI address lines are used to select the chip? I
guess that's more like traditional address decoding rather than chip
select. Anyway, understanding how your board design works helps devising
a device tree binding that is flexible enough to support production
devices.

Thierry

2016-07-25 13:59 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
>>
>
>> > +Note that the NOR controller does not have any internal chip-select address
>> > +decoding and if you want to access multiple devices external chip-select
>> > +decoding must be provided.
>>
>> Although it is true, you do have the MIO address space and so you could
>> support two devices via the SNOR address space and MIO address space
>> (assuming that the MIO can be used for the 2nd device).
>
> Now I'm even more confused. If the GMI controller itself can't select a
> chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
> that not select a specific chip?
>
>> Furthermore, if you do have external logic to support multiple devices
>> this would assume that the devices use the same timing and so are
>> probably the same type. It also assumes both can fit in the 256MB
>> address range. May be worth mentioning.
>
> Similarly if you switch between different devices, wouldn't you have to
> reprogram the timing registers if they are different?
>
> The way I remember this kind of interface to work (it's been a long time
> since I used one) is that in order to operate on a chip you need to
> acquire the bus first. Typically that would be an API exposed by the bus
> driver or some framework that the bus driver registers with. That API
> arbitrates between multiple devices on the bus and makes sure that the
> proper chip select is asserted and timing is programmed when you're
> granted access. A driver that has acquired the bus can then perform what
> operations they need and release the bus when done.
>
> SPI uses a mechanism like this, for example.
>
> Thierry

From my experience (maybe not as long as yours :)) but these kind of
things would be handled by the controller. At least with previous SOCs
that I have used, PXA270, PXA300 and i.MX SOCs.

That it has an address range per chip-select PIN and timing registers
per chip-select. And thus eliminating a need for a infrastructure or
framework.


Best regards,
Mirza
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On Mon, Jul 25, 2016 at 02:09:18PM +0100, Jon Hunter wrote:
> 
> On 25/07/16 13:10, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Thu, Jul 21, 2016 at 10:10:49PM +0200, Mirza Krak wrote:
> >> 2016-07-21 11:56 GMT+02:00 Jon Hunter <jonathanh@nvidia.com>:
> >>>> +
> >>>> +The NOR controller supports a number of memory types, including synchronous NOR,
> >>>> +asynchronous NOR, and other flash memories with similar interfaces, such as
> >>>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> >>>> +CAN chips, Wi-Fi chips etc.
> >>>
> >>> Nit-pick ... the Tegra documentation refers to this controller as the
> >>> GMI (general memory interface) or SNOR (sync-NOR) controller because it
> >>> is not just limited to NOR as you mentioned. I see references to GMI in
> >>> the Tegra pinctrl driver and so may be we should use this name.
> >>
> >> ACK.
> >>
> >>
> >>>> +Required properties:
> >>>> +
> >>>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> >>>
> >>> I see at least one difference at the register level between Tegra20 and
> >>> Tegra30 and so I think this should be something like ...
> >>>
> >>>  - compatible : Should contain one of the following:
> >>>         For Tegra20 must contain "nvidia,tegra20-gmi".
> >>>         For Tegra30 must contain "nvidia,tegra30-gmi".
> >>
> >> ACK. Just curious, which register was it? I only checked that they
> >> have the same count of registers.
> >>
> >>>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> >>>
> >>> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
> >>> that this should be nvidia,snor-config to be explicit. It might be nice
> >>> to also add a "nvidia,mio-config" while you are at it as well, however,
> >>> that could always be done later. If you do, then the
> >>> "nvidia,snor-config" becomes optional depending on whether you are using
> >>> the SNOR or MIO address space.
> >>
> >> ACK the nvidia,snor-config part, will though wait for further comments
> >> regarding what to do with the config registers, break-out or keep it
> >> is a one property / register.
> >>
> >> Regarding mio-config, not sure about if I would like to include that
> >> part in this stage. If you feel strongly about this we can do it. If
> >> it only comes to down to replicate the same configurations that we do
> >> for SNOR to MIO then I do not see much of a problem, but would like
> >> SNOR to be accepted and would not like the MIO part to halt this. But
> >> then again this up to you guys.
> > 
> > What's the difference between SNOR and MIO? Sorry if I'm being dense but
> > a quick look around the internet didn't yield anything related. I'd be
> > happy to read up if somebody can provide a link.
> 
> I am not sure where this term MIO comes from (may be an NVIDIA term),
> but from looking at the MIO_CONFIG register, it looks like a basic
> 16/32-bit interface with configurable read/write strobe timing. Does not
> support bursting or address/data multiplexing that the SNOR interface
> does. So may be it is used for interfacing to external devices such as
> FIFOs, UARTs, I2C expanders, etc.

Yes, looks like some sort of parallel interface to connect external
devices and make them act like MMIO. Perhaps MIO is supposed to be
"memory I/O". I've found some vague references to MIO == multi-I/O,
but that was always related to serial flash (essentially something
like QSPI).

Thierry

2016-07-25 15:27 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Mon, Jul 25, 2016 at 03:20:44PM +0200, Mirza Krak wrote:
>> 2016-07-25 13:36 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
>> > On Thu, Jul 21, 2016 at 11:26:09AM +0100, Jon Hunter wrote:
>> >>
>> >> On 20/07/16 20:28, Mirza Krak wrote:
>> >> > 2016-07-20 14:44 GMT+02:00 Rob Herring <robh@kernel.org>:
>> >> >> On Tue, Jul 19, 2016 at 03:36:34PM +0200, Mirza Krak wrote:
>> >> >>> From: Mirza Krak <mirza.krak@gmail.com>
>> >> >>>
>> >> >>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>> >> >>> Tegra30 SOCs
>> >> >>>
>> >> >>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>> >> >>> ---
>> >> >>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>> >> >>>  1 file changed, 73 insertions(+)
>> >> >>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >> >>>
>> >> >>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >> >>> new file mode 100644
>> >> >>> index 0000000..9ee4a66
>> >> >>> --- /dev/null
>> >> >>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>> >> >>> @@ -0,0 +1,73 @@
>> >> >>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
>> >> >>> +
>> >> >>> +The NOR controller supports a number of memory types, including synchronous NOR,
>> >> >>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>> >> >>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>> >> >>> +CAN chips, Wi-Fi chips etc.
>> >> >>> +
>> >> >>> +The actual devices are instantiated from the child nodes of a NOR node.
>> >> >>> +
>> >> >>> +Required properties:
>> >> >>> +
>> >> >>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>> >> >>> + - reg: Should contain NOR controller registers location and length.
>> >> >>> + - clocks: Must contain one entry, for the module clock.
>> >> >>> +   See ../clocks/clock-bindings.txt for details.
>> >> >>> + - resets : Must contain an entry for each entry in reset-names.
>> >> >>> +   See ../reset/reset.txt for details.
>> >> >>> + - reset-names : Must include the following entries:
>> >> >>> +  - nor
>> >> >>> + - #address-cells: Must be set to 2 to allow memory address translation
>> >> >>> + - #size-cells:      Must be set to 1 to allow CS address passing
>> >> >>> + - ranges: Must be set up to reflect the memory layout with four integer
>> >> >>> +             values for each chip-select line in use.
>> >> >>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>> >> >>> +
>> >> >>> +Note that the NOR controller does not have any internal chip-select address
>> >> >>> +decoding and if you want to access multiple devices external chip-select
>> >> >>> +decoding must be provided.
>> >> >>
>> >> >> Then what are the 2 chip selects in ranges?
>> >> >>
>> >> >> Rob
>> >> >
>> >> > Those two chip selects are actually a representation of a external
>> >> > decoding logic based on what we use on our board. Even though it the
>> >> > NOR controller only supports one single chip select I wanted to give
>> >> > an example on how one could create more chip-selects with an external
>> >> > logic and what it would look like in the device tree representation.
>> >>
>> >> Technically, the GMI/SNOR controller supports 8 chip-selects, however,
>> >> unlike some devices, it appears that software has to select the active
>> >> chip-select. Although this sounds odd, I believe that the idea is that
>> >> in order to support devices greater than 256MB (external address space
>> >> for available NOR/async devices) you can use the chip-selects to page
>> >> through memory greater than this 256MB range. At least that it my
>> >> (limited) understanding!
>> >
>> > Actually I had assumed that software would at some point need to select
>> > the active chip to switch between multiple connected chips. I suppose it
>> > could be possible to have multiple chips share the same chip-select and
>> > decode the address lines to determine whether they're being accessed or
>> > not.
>> >
>> > What I don't understand, and it's further complicated by the fact that
>> > external chip-selects are being used, is how does the controller get
>> > told what chip to select? It seems to me like it would always access the
>> > same chips because the SNOR_CONFIG_0 register is only ever written on
>> > ->probe().
>> >
>> > For external chip selects, how do they tie in with all this? Who gets to
>> > implement this logic? Wouldn't we need to abstract this away somehow so
>> > that we can support whatever board designers will come up with?
>> >
>> > Thierry
>>
>> You answered it your self :).
>>
>> >I suppose it
>> > could be possible to have multiple chips share the same chip-select and
>> > decode the address lines to determine whether they're being accessed or
>> > not.
>>
>> That is what we do and is what I refer to as external chip-selects.
>
> Okay, so there aren't actually chips or pins that serve as external chip
> selects, but rather the GMI address lines are used to select the chip? I
> guess that's more like traditional address decoding rather than chip
> select. Anyway, understanding how your board design works helps devising
> a device tree binding that is flexible enough to support production
> devices.
>
> Thierry

This is the most accurate descriptor.

> GMI address lines are used to select the chip

Best Regards
Mirza
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On 25/07/16 12:59, Thierry Reding wrote:
> * PGP Signed by an unknown key
> 
> On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
>>
>> On 19/07/16 14:36, Mirza Krak wrote:
>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>
>>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
>>> Tegra30 SOCs
>>>
>>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
>>> ---
>>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
>>>  1 file changed, 73 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>> new file mode 100644
>>> index 0000000..9ee4a66
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
>>> @@ -0,0 +1,73 @@
>>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
>>> +
>>> +The NOR controller supports a number of memory types, including synchronous NOR,
>>> +asynchronous NOR, and other flash memories with similar interfaces, such as
>>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
>>> +CAN chips, Wi-Fi chips etc.
>>
>> Nit-pick ... the Tegra documentation refers to this controller as the
>> GMI (general memory interface) or SNOR (sync-NOR) controller because it
>> is not just limited to NOR as you mentioned. I see references to GMI in
>> the Tegra pinctrl driver and so may be we should use this name.
>>
>>> +
>>> +The actual devices are instantiated from the child nodes of a NOR node.
>>> +
>>> +Required properties:
>>> +
>>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
>>
>> I see at least one difference at the register level between Tegra20 and
>> Tegra30 and so I think this should be something like ...
>>
>>  - compatible : Should contain one of the following:
>> 	For Tegra20 must contain "nvidia,tegra20-gmi".
>>  	For Tegra30 must contain "nvidia,tegra30-gmi".
>>
>>> + - reg: Should contain NOR controller registers location and length.
>>> + - clocks: Must contain one entry, for the module clock.
>>> +   See ../clocks/clock-bindings.txt for details.
>>> + - resets : Must contain an entry for each entry in reset-names.
>>> +   See ../reset/reset.txt for details.
>>> + - reset-names : Must include the following entries:
>>> +  - nor
>>> + - #address-cells: Must be set to 2 to allow memory address translation
>>> + - #size-cells:	Must be set to 1 to allow CS address passing
>>> + - ranges: Must be set up to reflect the memory layout with four integer
>>> + 		values for each chip-select line in use.
>>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
>>
>> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
>> that this should be nvidia,snor-config to be explicit. It might be nice
>> to also add a "nvidia,mio-config" while you are at it as well, however,
>> that could always be done later. If you do, then the
>> "nvidia,snor-config" becomes optional depending on whether you are using
>> the SNOR or MIO address space.
>>
>> Thierry, Stephen, do prefer all the fields on the config registers are
>> broken out? There are quite a few but I am not sure what we typically
>> recommend here?
> 
> As I said elsewhere, I prefer breaking the fields out into separate
> properties because that makes it a lot easier to write the DT. Rather
> than having to go and manually assemble 32-bit values for this register
> and the timing registers, it must be a lot easier to look at datasheets
> and copy the values into the corresponding DT properties.

That's what I thought :-)

>>> +Note that the NOR controller does not have any internal chip-select address
>>> +decoding and if you want to access multiple devices external chip-select
>>> +decoding must be provided.
>>
>> Although it is true, you do have the MIO address space and so you could
>> support two devices via the SNOR address space and MIO address space
>> (assuming that the MIO can be used for the 2nd device).
> 
> Now I'm even more confused. If the GMI controller itself can't select a
> chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
> that not select a specific chip?

So the GMI has 8 chip-selects and these can be used by either the SNOR
interface for MIO interface. As you mentioned the chip-select used for
the SNOR interface is configured by the field SNOR_SEL in the
SNOR_CONFIG and similarly the chip-select for the MIO interface is
configured by the MIO_SEL field in the MIO_CONFIG register.

Looking at the Tegra20 TRM, the SNOR interface is mapped to the address
range 0xd0000000-0xdfffffff and the MIO interface is mapped to the
address range 0xe0000000-0xefffffff. If chip-select 0 is used for SNOR
and chip-select 1 is used for MIO, you can support two devices at the
same time and they will be accessible via different address ranges.
Whether you can use the MIO interface for the 2nd device is another
question.

If you want to support two 256MB NOR devices on the SNOR interface, then
you would need to reconfigure the SNOR_CONFIG each time you swap between
the two devices.

>> Furthermore, if you do have external logic to support multiple devices
>> this would assume that the devices use the same timing and so are
>> probably the same type. It also assumes both can fit in the 256MB
>> address range. May be worth mentioning.
> 
> Similarly if you switch between different devices, wouldn't you have to
> reprogram the timing registers if they are different?

Yes.

> The way I remember this kind of interface to work (it's been a long time
> since I used one) is that in order to operate on a chip you need to
> acquire the bus first. Typically that would be an API exposed by the bus
> driver or some framework that the bus driver registers with. That API
> arbitrates between multiple devices on the bus and makes sure that the
> proper chip select is asserted and timing is programmed when you're
> granted access. A driver that has acquired the bus can then perform what
> operations they need and release the bus when done.
> 
> SPI uses a mechanism like this, for example.

That would make sense. However, I am not sure how that would work with
the client drivers, such as the CAN driver Mirza is using, that wishes
to read/write directly to the SNOR address space. I am guessing that SPI
works like I2C and buffers up the requests and performs them in sequence.

Jon

On Mon, Jul 25, 2016 at 03:30:34PM +0200, Mirza Krak wrote:
> 2016-07-25 13:59 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> > On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
> >>
> >
> >> > +Note that the NOR controller does not have any internal chip-select address
> >> > +decoding and if you want to access multiple devices external chip-select
> >> > +decoding must be provided.
> >>
> >> Although it is true, you do have the MIO address space and so you could
> >> support two devices via the SNOR address space and MIO address space
> >> (assuming that the MIO can be used for the 2nd device).
> >
> > Now I'm even more confused. If the GMI controller itself can't select a
> > chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
> > that not select a specific chip?
> >
> >> Furthermore, if you do have external logic to support multiple devices
> >> this would assume that the devices use the same timing and so are
> >> probably the same type. It also assumes both can fit in the 256MB
> >> address range. May be worth mentioning.
> >
> > Similarly if you switch between different devices, wouldn't you have to
> > reprogram the timing registers if they are different?
> >
> > The way I remember this kind of interface to work (it's been a long time
> > since I used one) is that in order to operate on a chip you need to
> > acquire the bus first. Typically that would be an API exposed by the bus
> > driver or some framework that the bus driver registers with. That API
> > arbitrates between multiple devices on the bus and makes sure that the
> > proper chip select is asserted and timing is programmed when you're
> > granted access. A driver that has acquired the bus can then perform what
> > operations they need and release the bus when done.
> >
> > SPI uses a mechanism like this, for example.
> >
> > Thierry
> 
> From my experience (maybe not as long as yours :)) but these kind of
> things would be handled by the controller. At least with previous SOCs
> that I have used, PXA270, PXA300 and i.MX SOCs.
> 
> That it has an address range per chip-select PIN and timing registers
> per chip-select. And thus eliminating a need for a infrastructure or
> framework.

Okay, so the controllers have a translation table that needs to be
programmed and which maps address ranges to chip-selects. That's a nifty
feature, but I think it's also fairly specialized. In such a setup there
doesn't need to be a concept of chip-selects in software because it's
all transparently handled by the controller. Effectively the only time a
chip-select is needed is during the initial programming of the
controller when the translation table is set up.

From a software point of view the devices are then addressed by memory
address alone, so they aren't on a "manually switched" bus using chip-
selects.

Thierry

On Mon, Jul 25, 2016 at 02:36:35PM +0100, Jon Hunter wrote:
> 
> On 25/07/16 12:59, Thierry Reding wrote:
> > * PGP Signed by an unknown key
> > 
> > On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
> >>
> >> On 19/07/16 14:36, Mirza Krak wrote:
> >>> From: Mirza Krak <mirza.krak@gmail.com>
> >>>
> >>> Document the devicetree bindings for NOR bus driver found on Tegra20 and
> >>> Tegra30 SOCs
> >>>
> >>> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> >>> ---
> >>>  .../devicetree/bindings/bus/nvidia,tegra20-nor.txt | 73 ++++++++++++++++++++++
> >>>  1 file changed, 73 insertions(+)
> >>>  create mode 100644 Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>> new file mode 100644
> >>> index 0000000..9ee4a66
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra20-nor.txt
> >>> @@ -0,0 +1,73 @@
> >>> +Device tree bindings for NVIDIA Tegra20/30 NOR Bus
> >>> +
> >>> +The NOR controller supports a number of memory types, including synchronous NOR,
> >>> +asynchronous NOR, and other flash memories with similar interfaces, such as
> >>> +MuxOneNAND. One could also connect high speed devices like FPGAs, DSPs,
> >>> +CAN chips, Wi-Fi chips etc.
> >>
> >> Nit-pick ... the Tegra documentation refers to this controller as the
> >> GMI (general memory interface) or SNOR (sync-NOR) controller because it
> >> is not just limited to NOR as you mentioned. I see references to GMI in
> >> the Tegra pinctrl driver and so may be we should use this name.
> >>
> >>> +
> >>> +The actual devices are instantiated from the child nodes of a NOR node.
> >>> +
> >>> +Required properties:
> >>> +
> >>> + - compatible: should be "nvidia,tegra20-nor", "nvidia,tegra30-nor"
> >>
> >> I see at least one difference at the register level between Tegra20 and
> >> Tegra30 and so I think this should be something like ...
> >>
> >>  - compatible : Should contain one of the following:
> >> 	For Tegra20 must contain "nvidia,tegra20-gmi".
> >>  	For Tegra30 must contain "nvidia,tegra30-gmi".
> >>
> >>> + - reg: Should contain NOR controller registers location and length.
> >>> + - clocks: Must contain one entry, for the module clock.
> >>> +   See ../clocks/clock-bindings.txt for details.
> >>> + - resets : Must contain an entry for each entry in reset-names.
> >>> +   See ../reset/reset.txt for details.
> >>> + - reset-names : Must include the following entries:
> >>> +  - nor
> >>> + - #address-cells: Must be set to 2 to allow memory address translation
> >>> + - #size-cells:	Must be set to 1 to allow CS address passing
> >>> + - ranges: Must be set up to reflect the memory layout with four integer
> >>> + 		values for each chip-select line in use.
> >>> + - nvidia,config: This property represents the SNOR_CONFIG_0 register.
> >>
> >> There is also a SNOR_MIO_CONFIG for the MIO address space and so I think
> >> that this should be nvidia,snor-config to be explicit. It might be nice
> >> to also add a "nvidia,mio-config" while you are at it as well, however,
> >> that could always be done later. If you do, then the
> >> "nvidia,snor-config" becomes optional depending on whether you are using
> >> the SNOR or MIO address space.
> >>
> >> Thierry, Stephen, do prefer all the fields on the config registers are
> >> broken out? There are quite a few but I am not sure what we typically
> >> recommend here?
> > 
> > As I said elsewhere, I prefer breaking the fields out into separate
> > properties because that makes it a lot easier to write the DT. Rather
> > than having to go and manually assemble 32-bit values for this register
> > and the timing registers, it must be a lot easier to look at datasheets
> > and copy the values into the corresponding DT properties.
> 
> That's what I thought :-)
> 
> >>> +Note that the NOR controller does not have any internal chip-select address
> >>> +decoding and if you want to access multiple devices external chip-select
> >>> +decoding must be provided.
> >>
> >> Although it is true, you do have the MIO address space and so you could
> >> support two devices via the SNOR address space and MIO address space
> >> (assuming that the MIO can be used for the 2nd device).
> > 
> > Now I'm even more confused. If the GMI controller itself can't select a
> > chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
> > that not select a specific chip?
> 
> So the GMI has 8 chip-selects and these can be used by either the SNOR
> interface for MIO interface. As you mentioned the chip-select used for
> the SNOR interface is configured by the field SNOR_SEL in the
> SNOR_CONFIG and similarly the chip-select for the MIO interface is
> configured by the MIO_SEL field in the MIO_CONFIG register.
> 
> Looking at the Tegra20 TRM, the SNOR interface is mapped to the address
> range 0xd0000000-0xdfffffff and the MIO interface is mapped to the
> address range 0xe0000000-0xefffffff. If chip-select 0 is used for SNOR
> and chip-select 1 is used for MIO, you can support two devices at the
> same time and they will be accessible via different address ranges.
> Whether you can use the MIO interface for the 2nd device is another
> question.
> 
> If you want to support two 256MB NOR devices on the SNOR interface, then
> you would need to reconfigure the SNOR_CONFIG each time you swap between
> the two devices.
> 
> >> Furthermore, if you do have external logic to support multiple devices
> >> this would assume that the devices use the same timing and so are
> >> probably the same type. It also assumes both can fit in the 256MB
> >> address range. May be worth mentioning.
> > 
> > Similarly if you switch between different devices, wouldn't you have to
> > reprogram the timing registers if they are different?
> 
> Yes.

Okay, good. I'm relieved that I wasn't completely mistaken about how
this kind of hardware works. =)

> > The way I remember this kind of interface to work (it's been a long time
> > since I used one) is that in order to operate on a chip you need to
> > acquire the bus first. Typically that would be an API exposed by the bus
> > driver or some framework that the bus driver registers with. That API
> > arbitrates between multiple devices on the bus and makes sure that the
> > proper chip select is asserted and timing is programmed when you're
> > granted access. A driver that has acquired the bus can then perform what
> > operations they need and release the bus when done.
> > 
> > SPI uses a mechanism like this, for example.
> 
> That would make sense. However, I am not sure how that would work with
> the client drivers, such as the CAN driver Mirza is using, that wishes
> to read/write directly to the SNOR address space. I am guessing that SPI
> works like I2C and buffers up the requests and performs them in sequence.

Yes, you would of course have to guard accesses by the drivers with
calls to an API that acquire and release the bus. Not that it's very
nice, but in the absence of automatic address to CS translation that
really is the only way to solve it (explicit chip-select).

It doesn't seem like we currently have infrastructure for it, but we
would need something like that to solve this in the general case.

Thierry

2016-07-25 15:39 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Mon, Jul 25, 2016 at 03:30:34PM +0200, Mirza Krak wrote:
>> 2016-07-25 13:59 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
>> > On Thu, Jul 21, 2016 at 10:56:44AM +0100, Jon Hunter wrote:
>> >>
>> >
>> >> > +Note that the NOR controller does not have any internal chip-select address
>> >> > +decoding and if you want to access multiple devices external chip-select
>> >> > +decoding must be provided.
>> >>
>> >> Although it is true, you do have the MIO address space and so you could
>> >> support two devices via the SNOR address space and MIO address space
>> >> (assuming that the MIO can be used for the 2nd device).
>> >
>> > Now I'm even more confused. If the GMI controller itself can't select a
>> > chip, what is the SNOR_SEL field in the SNOR_CONFIG_0 register for? Does
>> > that not select a specific chip?
>> >
>> >> Furthermore, if you do have external logic to support multiple devices
>> >> this would assume that the devices use the same timing and so are
>> >> probably the same type. It also assumes both can fit in the 256MB
>> >> address range. May be worth mentioning.
>> >
>> > Similarly if you switch between different devices, wouldn't you have to
>> > reprogram the timing registers if they are different?
>> >
>> > The way I remember this kind of interface to work (it's been a long time
>> > since I used one) is that in order to operate on a chip you need to
>> > acquire the bus first. Typically that would be an API exposed by the bus
>> > driver or some framework that the bus driver registers with. That API
>> > arbitrates between multiple devices on the bus and makes sure that the
>> > proper chip select is asserted and timing is programmed when you're
>> > granted access. A driver that has acquired the bus can then perform what
>> > operations they need and release the bus when done.
>> >
>> > SPI uses a mechanism like this, for example.
>> >
>> > Thierry
>>
>> From my experience (maybe not as long as yours :)) but these kind of
>> things would be handled by the controller. At least with previous SOCs
>> that I have used, PXA270, PXA300 and i.MX SOCs.
>>
>> That it has an address range per chip-select PIN and timing registers
>> per chip-select. And thus eliminating a need for a infrastructure or
>> framework.
>
> Okay, so the controllers have a translation table that needs to be
> programmed and which maps address ranges to chip-selects. That's a nifty
> feature, but I think it's also fairly specialized. In such a setup there
> doesn't need to be a concept of chip-selects in software because it's
> all transparently handled by the controller. Effectively the only time a
> chip-select is needed is during the initial programming of the
> controller when the translation table is set up.

Yes, and in some cases you can not "program" the map as it is fixed in hardware.
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On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
[...]
> > The above suggests that one of the CAN controllers gets mapped to an
> > address 0x48000000 and the other gets mapped to 0x48040000. But why do
> > we even need a chip-select at all in that case? If both chips don't use
> > any overlapping memory region, what good does the chip-select do?
> 
> If we take a look on similar controllers found on others SOCs they
> usually define an address range / chip-select.
> 
> Example (weim):
> ranges = <
> 0 0 0x10000000 0x02000000
> 1 0 0x12000000 0x01000000
> 2 0 0x13000000 0x01000000
> 3 0 0x14000000 0x01000000
> 4 0 0x15000000 0x01000000
> 5 0 0x16000000 0x01000000
> >;
> 
> Which means that you all ready have an address mapped to PIN function.
> 
> But Tegra GMI controller is a first for me, where you do not have this
> kind of setup in hardware. Usually you also have a timing register /
> chip-select so that you can connect different chip types.
> 
> The lack of hardware support do decode an address to a chip-select PIN
> function, we have implemented this our self externally.
> 
> We actually have 6 different chips connected to the GMI bus and the
> "ranges" would be:
>   ranges = <
>    0 0 0x48000000 0x00000100
>    1 0 0x48040000 0x00000100
>    2 0 0x48080000 0x00000100
>    3 0 0x480A0000 0x00000100
>    4 0 0x480C0000 0x00000100
>    5 0 0x480E0000 0x00000100
>   >;
> 
> And this not nothing complicated, small number of AND gates and that is it.
> 
> The chip-select signal is necessary for the access characteristics, so
> we need to translate an address to an chip-select so that the chip
> knows the host CPU wants to talk to it.
> 
> Do not know if I made anything more clear here :).

Yes, that clarifies many things. The presence of an external, address-
based chip-select is essential information in order to describe this
setup properly.

Given that the external chip select is entirely invisible to software, I
think a more accurate description of your setup would be:

	gmi@70090000 {
		...

		/* for the chip select */
		#address-cells = <1>;
		#size-cells = <0>;

		/*
		 * Technically this could be used to translate the range from
		 * 0x48000000 to 0x4fffffff into a different range, but that
		 * no longer works because of the #address-cells. Does this
		 * matter?
		 */
		ranges;

		bus@0 {
			compatible = "simple-bus";
			reg = <0>;

			#address-cells = <1>;
			#size-cells = <1>;

			can@48000000 {
				reg = <0x48000000 0x100>;
				...
			};

			can@48040000 {
				reg = <0x48040000 0x100>;
				...
			};
		};
	};

That omits any reference to the external chip select, which I think
makes sense because it's something that software is completely unaware
of.

Perhaps one important question: does your setup use the GMI's CS lines
in any way? Or does it simply get ignored?

If it gets ignored, I suppose one could encode this as a special case:

	gmi@70090000 {
		...

		/* simple address translation */
		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x48000000 0x48000000 0x08000000>;

		can@48000000 {
			...
			reg = <0x48000000 0x100>;
			...
		};

		can@48040000 {
			...
			reg = <0x48000000 0x100>;
			...
		};
	};

We could use that special case in order to make the driver behave in a
special way that suits your setup, namely without explicit chip-select.
The case where #size-cells = <0> could be treated as the explicit chip-
select case, that somebody could implement in the future if they need
it. All other cases could be treated as meaning that the chip-select is
automatically handled externally (like in your setup) and we simply
statically configure the controller with chip select 0 (kind of in the
way your current patch series does).

Rob, what do you think about the above?

> > Also, it seems to me that you'd have to program the SNOR_CONFIG_0
> > register in order to select a specific chip, but I don't see anything in
> > the driver access that register after the initial write of the register.
> 
> This is only setup at probe.
> 
> >
> > I would've expected this to require some sort of infrastructure to allow
> > devices connected to the GMI controller to acquire the bus via some API
> > to select their chip.
> 
> Yes, ultimately you would need some sort of infrastructure to allow
> devices to acquire the GMI bus if you want to solve this in software.
> But at the moment I do not see such an infrastructure in place, and is
> it feasible to add one specifically for the GMI controller? If one
> such infrastructure was in place we would need to modify all the
> drivers that want to use to include Tegra specific infrastructure to
> access the GMI bus?
> 
> Since my knowledge is limited it hard for me to comment on this, maybe
> there is a simple way of doing this?

I don't think there's a simple way to do this. In order to properly
implement it we'd need to implement a generic infrastructure for chip
selects so that drivers such as the one for your CAN controller can be
written without tying them specifically to the Tegra GMI controller.

From what you and Jon were saying it sounds like the drivers are
completely agnostic of any chip-select, so conversion won't be easy.
But technically if these chips take a chip-select as input then it's
always possible to hook them up to a controller that doesn't do this
automatic translation of address to chip-select, so eventually some
setup is bound to come along where they'd need explicit chip-select
handling as well.

I don't think it's fair to require you to implement this infrastructure
if you don't actually need it. At the same time I want to be cautious
and make sure we keep the driver and binding flexible enough to allow
us to implement explicit chip-selects should we later need them.

Thierry

2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
>> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> [...]
>> > The above suggests that one of the CAN controllers gets mapped to an
>> > address 0x48000000 and the other gets mapped to 0x48040000. But why do
>> > we even need a chip-select at all in that case? If both chips don't use
>> > any overlapping memory region, what good does the chip-select do?
>>
>> If we take a look on similar controllers found on others SOCs they
>> usually define an address range / chip-select.
>>
>> Example (weim):
>> ranges = <
>> 0 0 0x10000000 0x02000000
>> 1 0 0x12000000 0x01000000
>> 2 0 0x13000000 0x01000000
>> 3 0 0x14000000 0x01000000
>> 4 0 0x15000000 0x01000000
>> 5 0 0x16000000 0x01000000
>> >;
>>
>> Which means that you all ready have an address mapped to PIN function.
>>
>> But Tegra GMI controller is a first for me, where you do not have this
>> kind of setup in hardware. Usually you also have a timing register /
>> chip-select so that you can connect different chip types.
>>
>> The lack of hardware support do decode an address to a chip-select PIN
>> function, we have implemented this our self externally.
>>
>> We actually have 6 different chips connected to the GMI bus and the
>> "ranges" would be:
>>   ranges = <
>>    0 0 0x48000000 0x00000100
>>    1 0 0x48040000 0x00000100
>>    2 0 0x48080000 0x00000100
>>    3 0 0x480A0000 0x00000100
>>    4 0 0x480C0000 0x00000100
>>    5 0 0x480E0000 0x00000100
>>   >;
>>
>> And this not nothing complicated, small number of AND gates and that is it.
>>
>> The chip-select signal is necessary for the access characteristics, so
>> we need to translate an address to an chip-select so that the chip
>> knows the host CPU wants to talk to it.
>>
>> Do not know if I made anything more clear here :).
>
> Yes, that clarifies many things. The presence of an external, address-
> based chip-select is essential information in order to describe this
> setup properly.
>
> Given that the external chip select is entirely invisible to software, I
> think a more accurate description of your setup would be:
>
>         gmi@70090000 {
>                 ...
>
>                 /* for the chip select */
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>
>                 /*
>                  * Technically this could be used to translate the range from
>                  * 0x48000000 to 0x4fffffff into a different range, but that
>                  * no longer works because of the #address-cells. Does this
>                  * matter?
>                  */
>                 ranges;
>
>                 bus@0 {
>                         compatible = "simple-bus";
>                         reg = <0>;
>
>                         #address-cells = <1>;
>                         #size-cells = <1>;
>
>                         can@48000000 {
>                                 reg = <0x48000000 0x100>;
>                                 ...
>                         };
>
>                         can@48040000 {
>                                 reg = <0x48040000 0x100>;
>                                 ...
>                         };
>                 };
>         };
>
> That omits any reference to the external chip select, which I think
> makes sense because it's something that software is completely unaware
> of.
>
> Perhaps one important question: does your setup use the GMI's CS lines
> in any way? Or does it simply get ignored?

Yes, we use the GMI`s CS line. It is important that is present because
it is ANDED with address lines and NOT ALE line. Especially since we
run the GMI controller in AD_MUX mode, which means that we use same
pins for address and data and the access happens in two phases, one
address latch phase where CS is not asserted but ALE is, second
read/write phase where CS must be asserted. In this case we need the
GMI`s CS line to determine which phase we are in.

Will give above a test run.

>
> If it gets ignored, I suppose one could encode this as a special case:
>
>         gmi@70090000 {
>                 ...
>
>                 /* simple address translation */
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>
>                 ranges = <0x48000000 0x48000000 0x08000000>;
>
>                 can@48000000 {
>                         ...
>                         reg = <0x48000000 0x100>;
>                         ...
>                 };
>
>                 can@48040000 {
>                         ...
>                         reg = <0x48000000 0x100>;
>                         ...
>                 };
>         };
>
> We could use that special case in order to make the driver behave in a
> special way that suits your setup, namely without explicit chip-select.
> The case where #size-cells = <0> could be treated as the explicit chip-
> select case, that somebody could implement in the future if they need
> it. All other cases could be treated as meaning that the chip-select is
> automatically handled externally (like in your setup) and we simply
> statically configure the controller with chip select 0 (kind of in the
> way your current patch series does).
>
> Rob, what do you think about the above?
>
>> > Also, it seems to me that you'd have to program the SNOR_CONFIG_0
>> > register in order to select a specific chip, but I don't see anything in
>> > the driver access that register after the initial write of the register.
>>
>> This is only setup at probe.
>>
>> >
>> > I would've expected this to require some sort of infrastructure to allow
>> > devices connected to the GMI controller to acquire the bus via some API
>> > to select their chip.
>>
>> Yes, ultimately you would need some sort of infrastructure to allow
>> devices to acquire the GMI bus if you want to solve this in software.
>> But at the moment I do not see such an infrastructure in place, and is
>> it feasible to add one specifically for the GMI controller? If one
>> such infrastructure was in place we would need to modify all the
>> drivers that want to use to include Tegra specific infrastructure to
>> access the GMI bus?
>>
>> Since my knowledge is limited it hard for me to comment on this, maybe
>> there is a simple way of doing this?
>
> I don't think there's a simple way to do this. In order to properly
> implement it we'd need to implement a generic infrastructure for chip
> selects so that drivers such as the one for your CAN controller can be
> written without tying them specifically to the Tegra GMI controller.
>
> From what you and Jon were saying it sounds like the drivers are
> completely agnostic of any chip-select, so conversion won't be easy.
> But technically if these chips take a chip-select as input then it's
> always possible to hook them up to a controller that doesn't do this
> automatic translation of address to chip-select, so eventually some
> setup is bound to come along where they'd need explicit chip-select
> handling as well.
>
> I don't think it's fair to require you to implement this infrastructure
> if you don't actually need it. At the same time I want to be cautious
> and make sure we keep the driver and binding flexible enough to allow
> us to implement explicit chip-selects should we later need them.
>
> Thierry

I understand, and thank you for not requiring me to implement such a
infrastructure :)

And thank you for your feedback.

Best Regards,
Mirza
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On 25/07/16 15:38, Mirza Krak wrote:
> 2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
>> On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
>>> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
>> [...]
>>>> The above suggests that one of the CAN controllers gets mapped to an
>>>> address 0x48000000 and the other gets mapped to 0x48040000. But why do
>>>> we even need a chip-select at all in that case? If both chips don't use
>>>> any overlapping memory region, what good does the chip-select do?
>>>
>>> If we take a look on similar controllers found on others SOCs they
>>> usually define an address range / chip-select.
>>>
>>> Example (weim):
>>> ranges = <
>>> 0 0 0x10000000 0x02000000
>>> 1 0 0x12000000 0x01000000
>>> 2 0 0x13000000 0x01000000
>>> 3 0 0x14000000 0x01000000
>>> 4 0 0x15000000 0x01000000
>>> 5 0 0x16000000 0x01000000
>>>> ;
>>>
>>> Which means that you all ready have an address mapped to PIN function.
>>>
>>> But Tegra GMI controller is a first for me, where you do not have this
>>> kind of setup in hardware. Usually you also have a timing register /
>>> chip-select so that you can connect different chip types.
>>>
>>> The lack of hardware support do decode an address to a chip-select PIN
>>> function, we have implemented this our self externally.
>>>
>>> We actually have 6 different chips connected to the GMI bus and the
>>> "ranges" would be:
>>>   ranges = <
>>>    0 0 0x48000000 0x00000100
>>>    1 0 0x48040000 0x00000100
>>>    2 0 0x48080000 0x00000100
>>>    3 0 0x480A0000 0x00000100
>>>    4 0 0x480C0000 0x00000100
>>>    5 0 0x480E0000 0x00000100
>>>   >;
>>>
>>> And this not nothing complicated, small number of AND gates and that is it.
>>>
>>> The chip-select signal is necessary for the access characteristics, so
>>> we need to translate an address to an chip-select so that the chip
>>> knows the host CPU wants to talk to it.
>>>
>>> Do not know if I made anything more clear here :).
>>
>> Yes, that clarifies many things. The presence of an external, address-
>> based chip-select is essential information in order to describe this
>> setup properly.
>>
>> Given that the external chip select is entirely invisible to software, I
>> think a more accurate description of your setup would be:
>>
>>         gmi@70090000 {
>>                 ...
>>
>>                 /* for the chip select */
>>                 #address-cells = <1>;
>>                 #size-cells = <0>;
>>
>>                 /*
>>                  * Technically this could be used to translate the range from
>>                  * 0x48000000 to 0x4fffffff into a different range, but that
>>                  * no longer works because of the #address-cells. Does this
>>                  * matter?
>>                  */
>>                 ranges;
>>
>>                 bus@0 {
>>                         compatible = "simple-bus";
>>                         reg = <0>;
>>
>>                         #address-cells = <1>;
>>                         #size-cells = <1>;
>>
>>                         can@48000000 {
>>                                 reg = <0x48000000 0x100>;
>>                                 ...
>>                         };
>>
>>                         can@48040000 {
>>                                 reg = <0x48040000 0x100>;
>>                                 ...
>>                         };
>>                 };
>>         };
>>
>> That omits any reference to the external chip select, which I think
>> makes sense because it's something that software is completely unaware
>> of.
>>
>> Perhaps one important question: does your setup use the GMI's CS lines
>> in any way? Or does it simply get ignored?
> 
> Yes, we use the GMI`s CS line. It is important that is present because
> it is ANDED with address lines and NOT ALE line. Especially since we
> run the GMI controller in AD_MUX mode, which means that we use same
> pins for address and data and the access happens in two phases, one
> address latch phase where CS is not asserted but ALE is, second
> read/write phase where CS must be asserted. In this case we need the
> GMI`s CS line to determine which phase we are in.

Even though the CS is used, we could still implement the driver such
that if only 1 CS is defined in the binding, we then statically program
the configuration at probe. For now, if there is more than one, we can
return an error from probe as it is not supported or default to the
first CS defined and warn?

Jon

On Mon, Jul 25, 2016 at 04:01:49PM +0100, Jon Hunter wrote:
> 
> On 25/07/16 15:38, Mirza Krak wrote:
> > 2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> >> On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
> >>> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> >> [...]
> >>>> The above suggests that one of the CAN controllers gets mapped to an
> >>>> address 0x48000000 and the other gets mapped to 0x48040000. But why do
> >>>> we even need a chip-select at all in that case? If both chips don't use
> >>>> any overlapping memory region, what good does the chip-select do?
> >>>
> >>> If we take a look on similar controllers found on others SOCs they
> >>> usually define an address range / chip-select.
> >>>
> >>> Example (weim):
> >>> ranges = <
> >>> 0 0 0x10000000 0x02000000
> >>> 1 0 0x12000000 0x01000000
> >>> 2 0 0x13000000 0x01000000
> >>> 3 0 0x14000000 0x01000000
> >>> 4 0 0x15000000 0x01000000
> >>> 5 0 0x16000000 0x01000000
> >>>> ;
> >>>
> >>> Which means that you all ready have an address mapped to PIN function.
> >>>
> >>> But Tegra GMI controller is a first for me, where you do not have this
> >>> kind of setup in hardware. Usually you also have a timing register /
> >>> chip-select so that you can connect different chip types.
> >>>
> >>> The lack of hardware support do decode an address to a chip-select PIN
> >>> function, we have implemented this our self externally.
> >>>
> >>> We actually have 6 different chips connected to the GMI bus and the
> >>> "ranges" would be:
> >>>   ranges = <
> >>>    0 0 0x48000000 0x00000100
> >>>    1 0 0x48040000 0x00000100
> >>>    2 0 0x48080000 0x00000100
> >>>    3 0 0x480A0000 0x00000100
> >>>    4 0 0x480C0000 0x00000100
> >>>    5 0 0x480E0000 0x00000100
> >>>   >;
> >>>
> >>> And this not nothing complicated, small number of AND gates and that is it.
> >>>
> >>> The chip-select signal is necessary for the access characteristics, so
> >>> we need to translate an address to an chip-select so that the chip
> >>> knows the host CPU wants to talk to it.
> >>>
> >>> Do not know if I made anything more clear here :).
> >>
> >> Yes, that clarifies many things. The presence of an external, address-
> >> based chip-select is essential information in order to describe this
> >> setup properly.
> >>
> >> Given that the external chip select is entirely invisible to software, I
> >> think a more accurate description of your setup would be:
> >>
> >>         gmi@70090000 {
> >>                 ...
> >>
> >>                 /* for the chip select */
> >>                 #address-cells = <1>;
> >>                 #size-cells = <0>;
> >>
> >>                 /*
> >>                  * Technically this could be used to translate the range from
> >>                  * 0x48000000 to 0x4fffffff into a different range, but that
> >>                  * no longer works because of the #address-cells. Does this
> >>                  * matter?
> >>                  */
> >>                 ranges;
> >>
> >>                 bus@0 {
> >>                         compatible = "simple-bus";
> >>                         reg = <0>;
> >>
> >>                         #address-cells = <1>;
> >>                         #size-cells = <1>;
> >>
> >>                         can@48000000 {
> >>                                 reg = <0x48000000 0x100>;
> >>                                 ...
> >>                         };
> >>
> >>                         can@48040000 {
> >>                                 reg = <0x48040000 0x100>;
> >>                                 ...
> >>                         };
> >>                 };
> >>         };
> >>
> >> That omits any reference to the external chip select, which I think
> >> makes sense because it's something that software is completely unaware
> >> of.
> >>
> >> Perhaps one important question: does your setup use the GMI's CS lines
> >> in any way? Or does it simply get ignored?
> > 
> > Yes, we use the GMI`s CS line. It is important that is present because
> > it is ANDED with address lines and NOT ALE line. Especially since we
> > run the GMI controller in AD_MUX mode, which means that we use same
> > pins for address and data and the access happens in two phases, one
> > address latch phase where CS is not asserted but ALE is, second
> > read/write phase where CS must be asserted. In this case we need the
> > GMI`s CS line to determine which phase we are in.
> 
> Even though the CS is used, we could still implement the driver such
> that if only 1 CS is defined in the binding, we then statically program
> the configuration at probe. For now, if there is more than one, we can
> return an error from probe as it is not supported or default to the
> first CS defined and warn?

I think either would work. Possibly better to do the latter because at
least some devices will work that way.

Thierry

2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
>> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
>> >
>> > I would've expected this to require some sort of infrastructure to allow
>> > devices connected to the GMI controller to acquire the bus via some API
>> > to select their chip.
>>
>> Yes, ultimately you would need some sort of infrastructure to allow
>> devices to acquire the GMI bus if you want to solve this in software.
>> But at the moment I do not see such an infrastructure in place, and is
>> it feasible to add one specifically for the GMI controller? If one
>> such infrastructure was in place we would need to modify all the
>> drivers that want to use to include Tegra specific infrastructure to
>> access the GMI bus?
>>
>> Since my knowledge is limited it hard for me to comment on this, maybe
>> there is a simple way of doing this?
>
> I don't think there's a simple way to do this. In order to properly
> implement it we'd need to implement a generic infrastructure for chip
> selects so that drivers such as the one for your CAN controller can be
> written without tying them specifically to the Tegra GMI controller.
>
> From what you and Jon were saying it sounds like the drivers are
> completely agnostic of any chip-select, so conversion won't be easy.
> But technically if these chips take a chip-select as input then it's
> always possible to hook them up to a controller that doesn't do this
> automatic translation of address to chip-select, so eventually some
> setup is bound to come along where they'd need explicit chip-select
> handling as well.
>
> I don't think it's fair to require you to implement this infrastructure
> if you don't actually need it. At the same time I want to be cautious
> and make sure we keep the driver and binding flexible enough to allow
> us to implement explicit chip-selects should we later need them.
>
> Thierry

One thing that should be noted, and that is the GMI controller also
supports a DMA master mode (feature for the future?).

I do not really know how this effects the binding we are discussing
but wanted to put it out there.

Best Regards,
Mirza
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On Mon, Jul 25, 2016 at 09:59:34PM +0200, Mirza Krak wrote:
> 2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> > On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
> >> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> >> >
> >> > I would've expected this to require some sort of infrastructure to allow
> >> > devices connected to the GMI controller to acquire the bus via some API
> >> > to select their chip.
> >>
> >> Yes, ultimately you would need some sort of infrastructure to allow
> >> devices to acquire the GMI bus if you want to solve this in software.
> >> But at the moment I do not see such an infrastructure in place, and is
> >> it feasible to add one specifically for the GMI controller? If one
> >> such infrastructure was in place we would need to modify all the
> >> drivers that want to use to include Tegra specific infrastructure to
> >> access the GMI bus?
> >>
> >> Since my knowledge is limited it hard for me to comment on this, maybe
> >> there is a simple way of doing this?
> >
> > I don't think there's a simple way to do this. In order to properly
> > implement it we'd need to implement a generic infrastructure for chip
> > selects so that drivers such as the one for your CAN controller can be
> > written without tying them specifically to the Tegra GMI controller.
> >
> > From what you and Jon were saying it sounds like the drivers are
> > completely agnostic of any chip-select, so conversion won't be easy.
> > But technically if these chips take a chip-select as input then it's
> > always possible to hook them up to a controller that doesn't do this
> > automatic translation of address to chip-select, so eventually some
> > setup is bound to come along where they'd need explicit chip-select
> > handling as well.
> >
> > I don't think it's fair to require you to implement this infrastructure
> > if you don't actually need it. At the same time I want to be cautious
> > and make sure we keep the driver and binding flexible enough to allow
> > us to implement explicit chip-selects should we later need them.
> >
> > Thierry
> 
> One thing that should be noted, and that is the GMI controller also
> supports a DMA master mode (feature for the future?).
> 
> I do not really know how this effects the binding we are discussing
> but wanted to put it out there.

Yes, that had occurred to me as well. I don't really have any good ideas
on how to use that other than to implement it as a DMA engine driver and
have drivers use those, if available.

But I don't think we have to worry about it right now. If we ever need
it, the binding can be extended in a backwards-compatible way.

Thierry

2016-07-25 16:15 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> On Mon, Jul 25, 2016 at 03:16:28PM +0200, Mirza Krak wrote:
>> 2016-07-25 13:30 GMT+02:00 Thierry Reding <thierry.reding@gmail.com>:
> Yes, that clarifies many things. The presence of an external, address-
> based chip-select is essential information in order to describe this
> setup properly.
>
> Given that the external chip select is entirely invisible to software, I
> think a more accurate description of your setup would be:
>
>         gmi@70090000 {
>                 ...
>
>                 /* for the chip select */
>                 #address-cells = <1>;
>                 #size-cells = <0>;
>
>                 /*
>                  * Technically this could be used to translate the range from
>                  * 0x48000000 to 0x4fffffff into a different range, but that
>                  * no longer works because of the #address-cells. Does this
>                  * matter?
>                  */
>                 ranges;
>
>                 bus@0 {
>                         compatible = "simple-bus";
>                         reg = <0>;
>
>                         #address-cells = <1>;
>                         #size-cells = <1>;
>
>                         can@48000000 {
>                                 reg = <0x48000000 0x100>;
>                                 ...
>                         };
>
>                         can@48040000 {
>                                 reg = <0x48040000 0x100>;
>                                 ...
>                         };
>                 };
>         };
>

Finally got around to test this. Above example had some issues, or I
am doing something wrong.

First of, the address parser does not seem to like that #size-cells =
<0> when ranges are empty. Got following warning from device tree
compiler:
Warning (ranges_format): /nor@70009000 has empty "ranges" property but
its #size-cells (0) differs from / (1)

and on boot:
[    0.399357] prom_parse: Bad cell count for /nor@70009000/bus@0

Got it to work if I changed to (also had to add an empty ranges prop
in bus node):

gmi@70009000 {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;

    bus@0,0 {
                compatible = "simple-bus";
                reg = <0 0>;
                ranges;

                #address-cells = <1>;
                #size-cells = <1>;

                can@48000000 {
                    reg = <0x48000000 0x100>;
                    ...
                };


                can@48040000 {
                    reg = <0x48040000 0x100>;
                    ...
                };
}

But I wonder is there something wrong with below example (which does
work), that is omitting the bus node:

gmi@70009000 {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges;

    can@48000000 {
        reg = <0x48000000 0x100>;
        ...
    };

    can@48040000 {
        reg = <0x48040000 0x100>;
        ...
    };
}

Just feel that I need to duplicate information if add an bus node.

Best Regards,
Mirza
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