From patchwork Thu Jul 7 08:01:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 645804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rlW1g3SXzz9sdn for ; Thu, 7 Jul 2016 18:26:47 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b=MWB8+rf3; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933219AbcGGIZf (ORCPT ); Thu, 7 Jul 2016 04:25:35 -0400 Received: from mail-wm0-f42.google.com ([74.125.82.42]:35850 "EHLO mail-wm0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933483AbcGGIDh (ORCPT ); Thu, 7 Jul 2016 04:03:37 -0400 Received: by mail-wm0-f42.google.com with SMTP id f126so200133957wma.1 for ; Thu, 07 Jul 2016 01:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vRA7DYdnuP0guhhgJXku16VH1UxzLNTwJXAElbr/xkA=; b=MWB8+rf3RNb1xKf4VIlUNOYXZW4EHRFY+i76gUMdR4iKWlQHEUW/gXoUxmrvRRtNvc 8BFhUcYxDRFX5/6YUd+rZbuT3mgszQYjXqZSxiiPEOrlpYg75Vqyu0wgun/G6B4yQfqz DVIUVuWb8iGFG6tip3bzk7OoaDnbV3siWXIHI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vRA7DYdnuP0guhhgJXku16VH1UxzLNTwJXAElbr/xkA=; b=VjkIEAJ/ZxO4M77pnoIDUowhYftJHT55W39X2S10B6eETMjRfHCtLIiucsi65PDDVG RNLeQzqiVSo1RnOP3M+e20E+/S3p34PNTck5Yd6dCJ+/Ront8f8AGjiINala1Ns2hI+8 YHUQwIiuKP5LNfxX3o7xaY62MPWwK8R64iqE7Kl55qf6RbOtEihMdPc8Xp7C5uemhdBk DBIgmWZQ1ww0ahf99obXQD6zCfULdG0IYgiFKrjWCRXyEEHp35Crtfyj7dKfqWVGX0Be EEYqTQ/9BpOJL7q9PRhN6gTj1Vh6jA51Jx5ndkYyWjd2iyZYxqvGRTtSbYsTUHDHQGwD Og0w== X-Gm-Message-State: ALyK8tIe1wMxDuY/Wy4wd9438g0aNfQz7goD3D1q25sUutsXVqn1djZBnBFcsbzOMWYgtLP5 X-Received: by 10.194.82.36 with SMTP id f4mr24335537wjy.104.1467878616091; Thu, 07 Jul 2016 01:03:36 -0700 (PDT) Received: from localhost.localdomain (lft31-1-88-121-166-205.fbx.proxad.net. [88.121.166.205]) by smtp.gmail.com with ESMTPSA id v70sm51327wmf.18.2016.07.07.01.03.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Jul 2016 01:03:35 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de, daniel.lezcano@linaro.org Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH 43/93] clocksource/drivers/tegra20: Convert init function to return error Date: Thu, 7 Jul 2016 10:01:16 +0200 Message-Id: <1467878526-1238-43-git-send-email-daniel.lezcano@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467878526-1238-1-git-send-email-daniel.lezcano@linaro.org> References: <577E0BED.3020608@linaro.org> <1467878526-1238-1-git-send-email-daniel.lezcano@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The init functions do not return any error. They behave as the following: - panic, thus leading to a kernel crash while another timer may work and make the system boot up correctly or - print an error and let the caller unaware if the state of the system Change that by converting the init functions to return an error conforming to the CLOCKSOURCE_OF_RET prototype. Proper error handling (rollback, errno value) will be changed later case by case, thus this change just return back an error or success in the init function. Signed-off-by: Daniel Lezcano --- drivers/clocksource/tegra20_timer.c | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index 7b94ad2..543c37e 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -165,7 +165,7 @@ static struct irqaction tegra_timer_irq = { .dev_id = &tegra_clockevent, }; -static void __init tegra20_init_timer(struct device_node *np) +static int __init tegra20_init_timer(struct device_node *np) { struct clk *clk; unsigned long rate; @@ -174,13 +174,13 @@ static void __init tegra20_init_timer(struct device_node *np) timer_reg_base = of_iomap(np, 0); if (!timer_reg_base) { pr_err("Can't map timer registers\n"); - BUG(); + return -ENXIO; } tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); if (tegra_timer_irq.irq <= 0) { pr_err("Failed to map timer IRQ\n"); - BUG(); + return -EINVAL; } clk = of_clk_get(np, 0); @@ -211,10 +211,12 @@ static void __init tegra20_init_timer(struct device_node *np) sched_clock_register(tegra_read_sched_clock, 32, 1000000); - if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, 300, 32, + clocksource_mmio_readl_up); + if (ret) { pr_err("Failed to register clocksource\n"); - BUG(); + return ret; } tegra_delay_timer.read_current_timer = @@ -225,24 +227,26 @@ static void __init tegra20_init_timer(struct device_node *np) ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); if (ret) { pr_err("Failed to register timer IRQ: %d\n", ret); - BUG(); + return ret; } tegra_clockevent.cpumask = cpu_all_mask; tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_config_and_register(&tegra_clockevent, 1000000, 0x1, 0x1fffffff); + + return 0; } -CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); +CLOCKSOURCE_OF_DECLARE_RET(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -static void __init tegra20_init_rtc(struct device_node *np) +static int __init tegra20_init_rtc(struct device_node *np) { struct clk *clk; rtc_base = of_iomap(np, 0); if (!rtc_base) { pr_err("Can't map RTC registers"); - BUG(); + return -ENXIO; } /* @@ -255,6 +259,6 @@ static void __init tegra20_init_rtc(struct device_node *np) else clk_prepare_enable(clk); - register_persistent_clock(NULL, tegra_read_persistent_clock64); + return register_persistent_clock(NULL, tegra_read_persistent_clock64); } -CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +CLOCKSOURCE_OF_DECLARE_RET(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);