From patchwork Wed Jun 22 11:47:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 639128 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZNVp2NkSz9t0Y for ; Wed, 22 Jun 2016 22:01:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752714AbcFVMB1 (ORCPT ); Wed, 22 Jun 2016 08:01:27 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:20825 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752708AbcFVMBZ (ORCPT ); Wed, 22 Jun 2016 08:01:25 -0400 Received: from hkpgpgate101.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate101.nvidia.com id ; Wed, 22 Jun 2016 20:01:24 +0800 Received: from HKMAIL102.nvidia.com ([10.18.67.137]) by hkpgpgate101.nvidia.com (PGP Universal service); Wed, 22 Jun 2016 05:01:22 -0700 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Wed, 22 Jun 2016 05:01:22 -0700 Received: from DRBGMAIL102.nvidia.com (10.18.16.21) by HKMAIL102.nvidia.com (10.18.16.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 22 Jun 2016 12:01:20 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by DRBGMAIL102.nvidia.com (10.18.16.21) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 22 Jun 2016 12:01:18 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 22 Jun 2016 12:01:14 +0000 From: Laxman Dewangan To: , , , CC: , , , , "Laxman Dewangan" Subject: [PATCH 5/5] pwm: tegra: Add support for Tegra186 Date: Wed, 22 Jun 2016 17:17:23 +0530 Message-ID: <1466596043-27262-6-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> References: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra186 has PWM controller with only one output instead of 4 output in earlier generation SoCs. Add support for Tegra186 and find the number of PWM output based on driver data. Signed-off-by: Laxman Dewangan Reviewed-by: Alexandre Courbot --- drivers/pwm/pwm-tegra.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 49cefd5..5547e7d 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -37,7 +38,9 @@ #define PWM_SCALE_WIDTH 13 #define PWM_SCALE_SHIFT 0 -#define NUM_PWM 4 +struct tegra_pwm_hwdata { + int num_pwm; +}; struct tegra_pwm_chip { struct pwm_chip chip; @@ -47,6 +50,7 @@ struct tegra_pwm_chip { struct reset_control *rstc; void __iomem *mmio_base; + const struct tegra_pwm_hwdata *hw; }; static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip) @@ -172,9 +176,16 @@ static const struct pwm_ops tegra_pwm_ops = { static int tegra_pwm_probe(struct platform_device *pdev) { struct tegra_pwm_chip *pwm; + const struct tegra_pwm_hwdata *hwdata; struct resource *r; int ret; + hwdata = of_device_get_match_data(&pdev->dev); + if (!hwdata) { + dev_err(&pdev->dev, "Tegra PWM HW data not found\n"); + return -ENODEV; + } + pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL); if (!pwm) return -ENOMEM; @@ -200,10 +211,11 @@ static int tegra_pwm_probe(struct platform_device *pdev) } reset_control_reset(pwm->rstc); + pwm->hw = hwdata; pwm->chip.dev = &pdev->dev; pwm->chip.ops = &tegra_pwm_ops; pwm->chip.base = -1; - pwm->chip.npwm = NUM_PWM; + pwm->chip.npwm = pwm->hw->num_pwm; ret = pwmchip_add(&pwm->chip); if (ret < 0) { @@ -222,7 +234,7 @@ static int tegra_pwm_remove(struct platform_device *pdev) if (WARN_ON(!pc)) return -ENODEV; - for (i = 0; i < NUM_PWM; i++) { + for (i = 0; i < pc->hw->num_pwm; i++) { struct pwm_device *pwm = &pc->chip.pwms[i]; if (!pwm_is_enabled(pwm)) @@ -237,9 +249,18 @@ static int tegra_pwm_remove(struct platform_device *pdev) return pwmchip_remove(&pc->chip); } +static const struct tegra_pwm_hwdata tegra20_pwm_hw = { + .num_pwm = 4, +}; + +static const struct tegra_pwm_hwdata tegra186_pwm_hw = { + .num_pwm = 1, +}; + static const struct of_device_id tegra_pwm_of_match[] = { - { .compatible = "nvidia,tegra20-pwm" }, - { .compatible = "nvidia,tegra30-pwm" }, + { .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_hw }, + { .compatible = "nvidia,tegra30-pwm", .data = &tegra20_pwm_hw }, + { .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_hw, }, { } };