From patchwork Fri Jun 17 12:03:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 636962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rWJpQ1th2z9t1r for ; Fri, 17 Jun 2016 22:04:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932755AbcFQME1 (ORCPT ); Fri, 17 Jun 2016 08:04:27 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15761 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755398AbcFQMEZ (ORCPT ); Fri, 17 Jun 2016 08:04:25 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 17 Jun 2016 05:04:05 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 17 Jun 2016 05:01:36 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 17 Jun 2016 05:01:36 -0700 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 12:04:24 +0000 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 12:04:23 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 17 Jun 2016 12:04:23 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.21.132.108]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 17 Jun 2016 05:04:23 -0700 From: Jon Hunter To: Thierry Reding , David Airlie , Stephen Warren , Alexandre Courbot , Wolfram Sang , Linus Walleij , Rob Herring , Mark Rutland CC: , , , , , Jon Hunter Subject: [RFC PATCH 04/13] drm/tegra: Add sor-safe clock for DPAUX on Tegra210 Date: Fri, 17 Jun 2016 13:03:38 +0100 Message-ID: <1466165027-17917-5-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> References: <1466165027-17917-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org For Tegra210 the 'sor-safe' clock needs to be enabled when using DPAUX. Add support to the DPAUX driver for enabling this clock on Tegra210. Signed-off-by: Jon Hunter --- drivers/gpu/drm/tegra/dpaux.c | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/dpaux.c b/drivers/gpu/drm/tegra/dpaux.c index aa3a037fcd3b..d696a7e45935 100644 --- a/drivers/gpu/drm/tegra/dpaux.c +++ b/drivers/gpu/drm/tegra/dpaux.c @@ -37,6 +37,7 @@ struct tegra_dpaux { struct reset_control *rst; struct clk *clk_parent; + struct clk *clk_sor; struct clk *clk; struct regulator *vdd; @@ -340,18 +341,37 @@ static int tegra_dpaux_probe(struct platform_device *pdev) return PTR_ERR(dpaux->rst); } + if (of_device_is_compatible(pdev->dev.of_node, + "nvidia,tegra210-dpaux")) { + dpaux->clk_sor = devm_clk_get(&pdev->dev, "sor-safe"); + if (IS_ERR(dpaux->clk_sor)) { + dev_err(&pdev->dev, + "failed to get sor-safe clock: %ld\n", + PTR_ERR(dpaux->clk_sor)); + return PTR_ERR(dpaux->clk_sor); + } + + err = clk_prepare_enable(dpaux->clk_sor); + if (err < 0) { + dev_err(&pdev->dev, + "failed to enable sor-safe clock: %d\n", err); + return err; + } + } + dpaux->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(dpaux->clk)) { dev_err(&pdev->dev, "failed to get module clock: %ld\n", PTR_ERR(dpaux->clk)); - return PTR_ERR(dpaux->clk); + err = PTR_ERR(dpaux->clk); + goto disable_sor_clk; } err = clk_prepare_enable(dpaux->clk); if (err < 0) { dev_err(&pdev->dev, "failed to enable module clock: %d\n", err); - return err; + goto disable_sor_clk; } reset_control_deassert(dpaux->rst); @@ -434,6 +454,9 @@ disable_parent_clk: assert_reset: reset_control_assert(dpaux->rst); clk_disable_unprepare(dpaux->clk); +disable_sor_clk: + if (dpaux->clk_sor) + clk_disable_unprepare(dpaux->clk_sor); return err; } @@ -456,6 +479,8 @@ static int tegra_dpaux_remove(struct platform_device *pdev) clk_disable_unprepare(dpaux->clk_parent); reset_control_assert(dpaux->rst); clk_disable_unprepare(dpaux->clk); + if (dpaux->clk_sor) + clk_disable_unprepare(dpaux->clk_sor); return 0; }