From patchwork Fri Jun 3 20:22:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rhyland Klein X-Patchwork-Id: 629998 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rLwXq1LjBz9s2k for ; Sat, 4 Jun 2016 06:23:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932627AbcFCUXx (ORCPT ); Fri, 3 Jun 2016 16:23:53 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14450 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932615AbcFCUXw (ORCPT ); Fri, 3 Jun 2016 16:23:52 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 03 Jun 2016 13:23:50 -0700 Received: from HQMAIL105.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 03 Jun 2016 13:20:56 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 03 Jun 2016 13:20:56 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 3 Jun 2016 20:23:51 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 3 Jun 2016 20:23:51 +0000 Received: from rklein-work.nvidia.com (Not Verified[10.2.68.54]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 03 Jun 2016 13:23:51 -0700 From: Rhyland Klein To: Laxman Dewangan , Thierry Reding CC: Stephen Warren , Jon Hunter , Alexandre Courbot , Andrew Bresticker , , , , Rhyland Klein Subject: [PATCH] ARM64: boot: dts: Add regulators for Tegra210 Smaug Date: Fri, 3 Jun 2016 16:22:45 -0400 Message-ID: <1464985365-11612-1-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add regulators to the Tegra210 Smaug DTS file including support for the max77620 PMIC. Signed-off-by: Rhyland Klein --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 350 ++++++++++++++++++++++++++ 1 file changed, 350 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 4d89f4e02d98..fdca5b5d79e8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1,6 +1,7 @@ /dts-v1/; #include +#include #include #include "tegra210.dtsi" @@ -1327,6 +1328,269 @@ }; }; + i2c@7000d000 { + status = "okay"; + clock-frequency = <1000000>; + + max77620: max77620@3c { + compatible = "maxim,max77620"; + reg = <0x3c>; + interrupts = <0 86 IRQ_TYPE_NONE>; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&max77620_default>; + + max77620_default: pinmux@0 { + pin_gpio { + pins = "gpio0", "gpio1", "gpio2", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + /* + * GPIO3 is used to en_pp3300, and it is part of power + * sequence, So it must be sequenced up (automatically + * set by OTP) and down properly. + */ + pin_gpio3 { + pins = "gpio3"; + function = "fps-out"; + drive-open-drain = <1>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <4>; + maxim,active-fps-power-down-slot = <2>; + }; + + pin_gpio5_6_7 { + pins = "gpio5", "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + }; + + pin_32k { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + + fps { + fps0 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = ; + }; + + fps1 { + maxim,shutdown-fps-time-period-us = <5120>; + maxim,fps-event-source = ; + maxim,enable-sleep; + }; + + fps2 { + maxim,fps-event-source = ; + }; + }; + + regulators { + in-ldo0-1-supply = <&pp1350>; + in-ldo2-supply = <&pp3300>; + in-ldo3-5-supply = <&pp3300>; + in-ldo7-8-supply = <&pp1350>; + + ppvar_soc: sd0 { + regulator-name = "PPVAR_SOC"; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <146>; + regulator-disable-ramp-delay = <4080>; + regulator-ramp-delay = <27500>; + regulator-ramp-delay-scale = <300>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <1>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1100_sd1: sd1 { + regulator-name = "PP1100"; + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <130>; + regulator-disable-ramp-delay = <145800>; + regulator-ramp-delay = <27500>; + regulator-ramp-delay-scale = <300>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <5>; + maxim,active-fps-power-down-slot = <1>; + }; + + pp1350: sd2 { + regulator-name = "PP1350"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <176>; + regulator-disable-ramp-delay = <32000>; + regulator-ramp-delay = <27500>; + regulator-ramp-delay-scale = <350>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <2>; + maxim,active-fps-power-down-slot = <5>; + }; + + pp1800: sd3 { + regulator-name = "PP1800"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <242>; + regulator-disable-ramp-delay = <118000>; + regulator-ramp-delay = <27500>; + regulator-ramp-delay-scale = <360>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <3>; + maxim,active-fps-power-down-slot = <3>; + }; + + pp1200_avdd: ldo0 { + regulator-name = "PP1200_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <26>; + regulator-disable-ramp-delay = <626>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1200_rcam: ldo1 { + regulator-name = "PP1200_RCAM"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <22>; + regulator-disable-ramp-delay = <630>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp_ldo2: ldo2 { + regulator-name = "PP_LDO2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <62>; + regulator-disable-ramp-delay = <650>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp2800l_rcam: ldo3 { + regulator-name = "PP2800L_RCAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <50>; + regulator-disable-ramp-delay = <1110>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp100_soc_rtc: ldo4 { + regulator-name = "PP1100_SOC_RTC"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-enable-ramp-delay = <22>; + regulator-disable-ramp-delay = <610>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + regulator-always-on; /* Check this */ + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <1>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp2800l_fcam: ldo5 { + regulator-name = "PP2800L_FCAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <62>; + regulator-disable-ramp-delay = <640>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + ldo6 { + /* Unused. */ + regulator-name = "PP_LDO6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <36>; + regulator-disable-ramp-delay = <674>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + + pp1050_avdd: ldo7 { + regulator-name = "PP1050_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <24>; + regulator-disable-ramp-delay = <2768>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + regulator-always-on; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <3>; + maxim,active-fps-power-down-slot = <4>; + }; + + avddio_1v05: ldo8 { + regulator-name = "AVDDIO_1V05"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <22>; + regulator-disable-ramp-delay = <1160>; + regulator-ramp-delay = <100000>; + regulator-ramp-delay-scale = <200>; + regulator-boot-on; + maxim,active-fps-source = ; + maxim,active-fps-power-up-slot = <0>; + maxim,active-fps-power-down-slot = <7>; + }; + }; + }; + }; + pmc@7000e400 { nvidia,invert-interrupt; nvidia,suspend-mode = <0>; @@ -1421,4 +1685,90 @@ compatible = "arm,psci-1.0"; method = "smc"; }; + + regulators { + compatible = "simple-bus"; + device_type = "fixed-regulators"; + #address-cells = <1>; + #size-cells = <0>; + + ppvar_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "PPVAR_SYS"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + regulator-always-on; + }; + + pplcd_vdd: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "PPLCD_VDD"; + regulator-min-microvolt = <4400000>; + regulator-max-microvolt = <4400000>; + gpio = <&gpio TEGRA_GPIO(V, 4) 0>; + enable-active-high; + regulator-boot-on; + }; + + pp3000_always: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "PP3000_ALWAYS"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + pp3300: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PP3300"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + gpio = <&max77620 3 0>; + enable-active-high; + }; + + pp5000: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "PP5000"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + pp1800_lcdio: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "PP1800_LCDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(V, 3) 0>; + enable-active-high; + regulator-boot-on; + }; + + pp1800_cam: regulator@6 { + compatible = "regulator-fixed"; + reg= <6>; + regulator-name = "PP1800_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio TEGRA_GPIO(K, 3) 0>; + enable-active-high; + }; + + usbc_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "USBC_VBUS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; };