From patchwork Fri May 6 10:45:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 619254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3r1TKm6Yz4z9t3r for ; Fri, 6 May 2016 20:58:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758272AbcEFK60 (ORCPT ); Fri, 6 May 2016 06:58:26 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12531 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758258AbcEFK6Y (ORCPT ); Fri, 6 May 2016 06:58:24 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 06 May 2016 03:57:46 -0700 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 06 May 2016 03:57:09 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 06 May 2016 03:57:09 -0700 Received: from DRUKMAIL102.nvidia.com (10.25.59.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 6 May 2016 10:58:22 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by drukmail102.nvidia.com (10.25.59.20) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 6 May 2016 10:58:17 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 6 May 2016 10:58:14 +0000 From: Laxman Dewangan To: , , , , CC: , , , Laxman Dewangan Subject: [PATCH V4 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Date: Fri, 6 May 2016 16:15:47 +0530 Message-ID: <1462531548-12914-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1462531548-12914-1-git-send-email-ldewangan@nvidia.com> References: <1462531548-12914-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan Reviewed-by: Jon Hunter --- Changes from V1: -This is new in series as per discussion on V1 series to use u32 for tegra_pmc_readl. Changes from V2: - Make unsigned long to u32 for some missed variable from V1. Changes from V3: - Revert back the value to ulong where time calcualtion is done. --- drivers/soc/tegra/pmc.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 2c3f1f9..09c2b97 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -875,10 +875,10 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request, return 0; } -static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, - unsigned long val, unsigned long timeout) +static int tegra_io_rail_poll(unsigned long offset, u32 mask, + u32 val, unsigned long timeout) { - unsigned long value; + u32 value; timeout = jiffies + msecs_to_jiffies(timeout); @@ -900,8 +900,9 @@ static void tegra_io_rail_unprepare(void) int tegra_io_rail_power_on(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; + u32 value, mask; int err; mutex_lock(&pmc->powergates_lock); @@ -935,8 +936,9 @@ EXPORT_SYMBOL(tegra_io_rail_power_on); int tegra_io_rail_power_off(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; + u32 value, mask; int err; mutex_lock(&pmc->powergates_lock);