From patchwork Fri Dec 4 14:57:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 552754 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 78C9F1402E2 for ; Sat, 5 Dec 2015 02:04:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753628AbbLDPAb (ORCPT ); Fri, 4 Dec 2015 10:00:31 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5525 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753745AbbLDPA1 (ORCPT ); Fri, 4 Dec 2015 10:00:27 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 04 Dec 2015 07:00:32 -0800 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 04 Dec 2015 06:57:22 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 04 Dec 2015 06:57:22 -0800 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.406.0; Fri, 4 Dec 2015 07:00:26 -0800 From: Jon Hunter To: Philipp Zabel , Stephen Warren , Thierry Reding , Alexandre Courbot , Rafael Wysocki , Kevin Hilman , Ulf Hansson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala CC: Vince Hsu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Jon Hunter Subject: [PATCH V4 06/16] soc: tegra: pmc: Wait for powergate state to change Date: Fri, 4 Dec 2015 14:57:07 +0000 Message-ID: <1449241037-22193-7-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> References: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Currently, the function tegra_powergate_set() simply sets the desired powergate state but does not wait for the state to change. In most cases we should wait for the state to change before proceeding. Currently, there is a case for tegra114 and tegra124 devices where we do not wait when starting the secondary CPU as this is not necessary. However, this is only done at boot time and so waiting here will only have a small impact on boot time. Therefore, update tegra_powergate_set() to wait when setting the powergate. By adding this feature, we can also eliminate the polling loop from tegra30_boot_secondary(). A macro has also been adding for checking the status of the powergate and so update the tegra_powergate_is_powered() to use this macro as well. Signed-off-by: Jon Hunter --- arch/arm/mach-tegra/platsmp.c | 16 +++------------- drivers/soc/tegra/pmc.c | 21 +++++++++++++++------ 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index b45086666648..40cb761e7c95 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -108,19 +108,9 @@ static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) * be un-gated by un-toggling the power gate register * manually. */ - if (!tegra_pmc_cpu_is_powered(cpu)) { - ret = tegra_pmc_cpu_power_on(cpu); - if (ret) - return ret; - - /* Wait for the power to come up. */ - timeout = jiffies + msecs_to_jiffies(100); - while (!tegra_pmc_cpu_is_powered(cpu)) { - if (time_after(jiffies, timeout)) - return -ETIMEDOUT; - udelay(10); - } - } + ret = tegra_pmc_cpu_power_on(cpu); + if (ret) + return ret; remove_clamps: /* CPU partition is powered. Enable the CPU clock. */ diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index fdd1a8d0940f..f94d970089ce 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -101,6 +102,8 @@ #define GPU_RG_CNTRL 0x2d4 +#define PMC_PWRGATE_STATE(status, id) ((status & BIT(id)) != 0) + struct tegra_pmc_soc { unsigned int num_powergates; const char *const *powergates; @@ -181,22 +184,27 @@ static void tegra_pmc_writel(u32 value, unsigned long offset) */ static int tegra_powergate_set(int id, bool new_state) { - bool status; + u32 status; + int err = 0; mutex_lock(&pmc->powergates_lock); - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); + status = tegra_pmc_readl(PWRGATE_STATUS); - if (status == new_state) { + if (PMC_PWRGATE_STATE(status, id) == new_state) { mutex_unlock(&pmc->powergates_lock); return 0; } tegra_pmc_writel(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); + err = readx_poll_timeout(tegra_pmc_readl, PWRGATE_STATUS, status, + PMC_PWRGATE_STATE(status, id) == new_state, + 10, 100000); + mutex_unlock(&pmc->powergates_lock); - return 0; + return err; } /** @@ -235,8 +243,9 @@ int tegra_powergate_is_powered(int id) if (!pmc->soc || id < 0 || id >= pmc->soc->num_powergates) return -EINVAL; - status = tegra_pmc_readl(PWRGATE_STATUS) & (1 << id); - return !!status; + status = tegra_pmc_readl(PWRGATE_STATUS); + + return PMC_PWRGATE_STATE(status, id); } /**