From patchwork Mon Oct 26 05:47:37 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 535698 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id F0B4C141351 for ; Mon, 26 Oct 2015 16:47:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753138AbbJZFrr (ORCPT ); Mon, 26 Oct 2015 01:47:47 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6545 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753143AbbJZFrq (ORCPT ); Mon, 26 Oct 2015 01:47:46 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 25 Oct 2015 22:47:07 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Sun, 25 Oct 2015 22:38:23 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Sun, 25 Oct 2015 22:38:23 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Sun, 25 Oct 2015 22:47:46 -0700 From: Alexandre Courbot To: Ben Skeggs CC: nouveau@lists.freedesktop.org, linux-tegra@vger.kernel.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH 3/3] gm20b: secure-boot FECS falcon Date: Mon, 26 Oct 2015 14:47:37 +0900 Message-ID: <1445838457-26737-2-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1445838457-26737-1-git-send-email-acourbot@nvidia.com> References: <1445838457-26737-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Enable secure boot of FECS for GM20B. Signed-off-by: Alexandre Courbot --- drm/nouveau/nvkm/engine/device/base.c | 4 ++++ drm/nouveau/nvkm/engine/gr/gm20b.c | 6 ++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index 3e26fc5431d7..94ffc005c2cc 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm/engine/device/base.c @@ -2043,6 +2043,10 @@ nv12b_chipset = { .fifo = gm20b_fifo_new, .gr = gm20b_gr_new, .sw = gf100_sw_new, + .secure_boot = { + .managed_falcons = BIT(LSF_FALCON_ID_FECS), + .boot_falcon = LSF_FALCON_ID_PMU, + }, }; static int diff --git a/drm/nouveau/nvkm/engine/gr/gm20b.c b/drm/nouveau/nvkm/engine/gr/gm20b.c index 65b6e3d1e90d..eabac5d1e44b 100644 --- a/drm/nouveau/nvkm/engine/gr/gm20b.c +++ b/drm/nouveau/nvkm/engine/gr/gm20b.c @@ -32,12 +32,10 @@ gm20b_gr_init_gpc_mmu(struct gf100_gr *gr) struct nvkm_device *device = gr->base.engine.subdev.device; u32 val; - /* TODO this needs to be removed once secure boot works */ - if (1) { + /* Bypass MMU check for non-secure boot */ + if (!device->chip->secure_boot.managed_falcons) nvkm_wr32(device, 0x100ce4, 0xffffffff); - } - /* TODO update once secure boot works */ val = nvkm_rd32(device, 0x100c80); val &= 0xf000087f; nvkm_wr32(device, 0x418880, val);