From patchwork Mon Oct 26 05:47:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 535697 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 488D7141352 for ; Mon, 26 Oct 2015 16:47:48 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753144AbbJZFrq (ORCPT ); Mon, 26 Oct 2015 01:47:46 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6540 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753138AbbJZFrp (ORCPT ); Mon, 26 Oct 2015 01:47:45 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 25 Oct 2015 22:47:05 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp08.nvidia.com (PGP Universal service); Sun, 25 Oct 2015 22:46:04 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Sun, 25 Oct 2015 22:46:04 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Sun, 25 Oct 2015 22:47:43 -0700 From: Alexandre Courbot To: Ben Skeggs CC: nouveau@lists.freedesktop.org, linux-tegra@vger.kernel.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH 2/3] gr: support for securely-booted FECS firmware Date: Mon, 26 Oct 2015 14:47:36 +0900 Message-ID: <1445838457-26737-1-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.6.1 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Trigger the loading of FECS/GPCCS using secure boot if required, and start managed falcons using the CPUCTL_ALIAS register since CPUCTL is protected in that case. Signed-off-by: Alexandre Courbot --- drm/nouveau/nvkm/engine/gr/gf100.c | 56 +++++++++++++++++++++++++++++++------- 1 file changed, 46 insertions(+), 10 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c index dda7a7d224c9..67691941d7ba 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -1342,16 +1343,40 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr) if (gr->firmware) { /* load fuc microcode */ nvkm_mc_unk260(device->mc, 0); - gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d); - gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad); + + if (nvkm_is_secure(device, LSF_FALCON_ID_FECS) || + nvkm_is_secure(device, LSF_FALCON_ID_GPCCS)) { + int err = nvkm_secure_boot(subdev->device); + + if (err) + return err; + } + + if (!nvkm_is_secure(device, LSF_FALCON_ID_FECS)) + gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, + &gr->fuc409d); + + if (!nvkm_is_secure(device, LSF_FALCON_ID_GPCCS)) + gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, + &gr->fuc41ad); + nvkm_mc_unk260(device->mc, 1); /* start both of them running */ nvkm_wr32(device, 0x409840, 0xffffffff); nvkm_wr32(device, 0x41a10c, 0x00000000); nvkm_wr32(device, 0x40910c, 0x00000000); - nvkm_wr32(device, 0x41a100, 0x00000002); - nvkm_wr32(device, 0x409100, 0x00000002); + /* Use FALCON_CPUCTL_ALIAS if falcon is in secure mode */ + if (nvkm_rd32(device, 0x41a100) & 0x40) + nvkm_wr32(device, 0x41a130, 0x00000002); + else + nvkm_wr32(device, 0x41a100, 0x00000002); + + /* Use FALCON_CPUCTL_ALIAS if falcon is in secure mode */ + if (nvkm_rd32(device, 0x409100) & 0x40) + nvkm_wr32(device, 0x409130, 0x00000002); + else + nvkm_wr32(device, 0x409100, 0x00000002); if (nvkm_msec(device, 2000, if (nvkm_rd32(device, 0x409800) & 0x00000001) break; @@ -1659,6 +1684,7 @@ int gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, int index, struct gf100_gr *gr) { + struct nvkm_subdev *subdev = &gr->base.engine.subdev; int ret; gr->func = func; @@ -1672,12 +1698,22 @@ gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device, return ret; if (gr->firmware) { - nvkm_info(&gr->base.engine.subdev, "using external firmware\n"); - if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || - gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) || - gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || - gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) - return -ENODEV; + nvkm_info(subdev, "using external firmware\n"); + if (!nvkm_is_secure(device, LSF_FALCON_ID_FECS)) { + if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) || + gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d)) + return -ENODEV; + } else { + nvkm_info(subdev, "FECS firmware securely managed\n"); + } + + if (!nvkm_is_secure(device, LSF_FALCON_ID_GPCCS)) { + if (gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) || + gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad)) + return -ENODEV; + } else { + nvkm_info(subdev, "GPCCS firmware securely managed\n"); + } } return 0;