From patchwork Wed Jul 1 09:13:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 489980 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id CB63F1402B2 for ; Wed, 1 Jul 2015 19:14:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753390AbbGAJOO (ORCPT ); Wed, 1 Jul 2015 05:14:14 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15055 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753195AbbGAJON (ORCPT ); Wed, 1 Jul 2015 05:14:13 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 01 Jul 2015 02:14:54 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 01 Jul 2015 02:14:10 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 01 Jul 2015 02:14:10 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Wed, 1 Jul 2015 02:14:10 -0700 From: Alexandre Courbot To: Thierry Reding , Stephen Warren CC: linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, gnurou@gmail.com, Alexandre Courbot Subject: [PATCH 3/4] ARM: tegra: jetson-tk1: Add GK20A GPU DT node Date: Wed, 1 Jul 2015 18:13:47 +0900 Message-ID: <1435742028-8237-4-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1435742028-8237-1-git-send-email-acourbot@nvidia.com> References: <1435742028-8237-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsability of the bootloader to enable it if the VPR registers have been programmed such as the GPU can operate. Signed-off-by: Alexandre Courbot --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index ed8a8acd3d34..f0459ea94981 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -53,6 +53,14 @@ }; }; + gpu@0,57000000 { + /* + * Node left disabled on purpose - the bootloader will enable + * it after having set the VPR up + */ + vdd-supply = <&vdd_gpu>; + }; + pinmux: pinmux@0,70000868 { pinctrl-names = "boot"; pinctrl-0 = <&state_boot>; @@ -1514,7 +1522,7 @@ regulator-always-on; }; - sd6 { + vdd_gpu: sd6 { regulator-name = "+VDD_GPU_AP"; regulator-min-microvolt = <650000>; regulator-max-microvolt = <1200000>;