From patchwork Tue Jun 23 06:16:01 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 487517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 532A714010F for ; Tue, 23 Jun 2015 16:17:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751445AbbFWGRY (ORCPT ); Tue, 23 Jun 2015 02:17:24 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:19229 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751463AbbFWGQa (ORCPT ); Tue, 23 Jun 2015 02:16:30 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Mon, 22 Jun 2015 23:16:50 -0700 Received: from hqemhub03.nvidia.com ([172.20.150.15]) by hqnvupgp07.nvidia.com (PGP Universal service); Mon, 22 Jun 2015 23:13:16 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Mon, 22 Jun 2015 23:13:16 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.342.0; Mon, 22 Jun 2015 23:16:29 -0700 From: Alexandre Courbot To: Ben Skeggs , , Andy Ritger , Aaron Plattner , Allen Martin , Ken Adams , Terje Bergstrom CC: , , , Alexandre Courbot Subject: [PATCH v2 1/6] gr: use NVIDIA-provided external firmwares Date: Tue, 23 Jun 2015 15:16:01 +0900 Message-ID: <1435040166-25651-2-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 2.4.4 In-Reply-To: <1435040166-25651-1-git-send-email-acourbot@nvidia.com> References: <1435040166-25651-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA will officially start providing GR firmwares through linux-firmware for GPUs that require it. Change the GR firmware lookup function to use these files. Signed-off-by: Alexandre Courbot --- drm/nouveau/nvkm/engine/gr/gf100.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drm/nouveau/nvkm/engine/gr/gf100.c b/drm/nouveau/nvkm/engine/gr/gf100.c index ca11ddb6ed46..454080339572 100644 --- a/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drm/nouveau/nvkm/engine/gr/gf100.c @@ -1550,18 +1550,25 @@ gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname, { struct nvkm_device *device = nv_device(priv); const struct firmware *fw; - char f[32]; + char f[64]; + char cname[16]; int ret; + int i; + + /* Convert device name to lowercase */ + strncpy(cname, device->cname, sizeof(cname)); + cname[sizeof(cname) - 1] = '\0'; + i = strlen(cname); + while (i) { + --i; + cname[i] = tolower(cname[i]); + } - snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname); + snprintf(f, sizeof(f), "nvidia/%s/%s.bin", cname, fwname); ret = request_firmware(&fw, f, nv_device_base(device)); if (ret) { - snprintf(f, sizeof(f), "nouveau/%s", fwname); - ret = request_firmware(&fw, f, nv_device_base(device)); - if (ret) { - nv_error(priv, "failed to load %s\n", fwname); - return ret; - } + nv_error(priv, "failed to load %s\n", fwname); + return ret; } fuc->size = fw->size; @@ -1615,10 +1622,10 @@ gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (use_ext_fw) { nv_info(priv, "using external firmware\n"); - if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) || - gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) || - gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) || - gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad)) + if (gf100_gr_ctor_fw(priv, "fecs_inst", &priv->fuc409c) || + gf100_gr_ctor_fw(priv, "fecs_data", &priv->fuc409d) || + gf100_gr_ctor_fw(priv, "gpccs_inst", &priv->fuc41ac) || + gf100_gr_ctor_fw(priv, "gpccs_data", &priv->fuc41ad)) return -ENODEV; priv->firmware = true; }