From patchwork Wed May 13 14:13:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 471932 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A26BE14016A for ; Thu, 14 May 2015 00:15:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965352AbbEMON5 (ORCPT ); Wed, 13 May 2015 10:13:57 -0400 Received: from mail-pd0-f201.google.com ([209.85.192.201]:33760 "EHLO mail-pd0-f201.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965351AbbEMONv (ORCPT ); Wed, 13 May 2015 10:13:51 -0400 Received: by pdjg10 with SMTP id g10so3043062pdj.0 for ; Wed, 13 May 2015 07:13:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=I3qK2svQyiEpT7RdBklkE/x77AtSpwtTx6MzwzUPL24=; b=anbmbOc9H33pU3xaawhHIUiIfU4fWEXF900afKcKUyv0qu3qHRWxMhGUVjVLEkQuPn Rut7A4GC/oNBQcX+jI2diepRkAK1Tyq/K2nKjdWcvZL3DXbOr30SzgIZPg7+41XOGbJX SlsH7K+maQrQxc4HmV0AIV0YNKJsKvgwn+qyLq6xWs9xbLWl5NmBEinfLebF3/S9Y5CW aVeF3joydiSdHfSA6jGWMa2gUhEvMVhGrXphz0wAoHU4Yjp/19EHGcELpKW+9ZspYYrG GeFy/2eGc+4yxX2Vjqd7761LOLSUgQekYrTUTYfGqTl9YV1v4Tctw85I1o6qJvYJ57uK CoLA== X-Gm-Message-State: ALoCoQnookZAObjyUBAcQSIQJBRblBEJHwNGAMxa9Ch2Eya+ejDrJyew5IlSq0MrCt5S71n5pUvj X-Received: by 10.66.164.73 with SMTP id yo9mr29008991pab.1.1431526430595; Wed, 13 May 2015 07:13:50 -0700 (PDT) Received: from corpmail-nozzle1-2.hot.corp.google.com ([100.108.1.103]) by gmr-mx.google.com with ESMTPS id l36si1091143yhb.1.2015.05.13.07.13.49 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2015 07:13:50 -0700 (PDT) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-2.hot.corp.google.com with ESMTP id 5YgR3ITM.1; Wed, 13 May 2015 07:13:50 -0700 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 3B1B42202F5; Wed, 13 May 2015 08:13:49 -0600 (MDT) From: Simon Glass To: LKML Cc: Stephen Warren , Stephen Warren , Simon Glass , Russell King , Thierry Reding , devicetree@vger.kernel.org, Kumar Gala , Ian Campbell , Rob Herring , Pawel Moll , linux-tegra@vger.kernel.org, Mark Rutland , Alexandre Courbot , linux-arm-kernel@lists.infradead.org Subject: [PATCH] ARM: tegra: Enable TPM on tegra124 nyan boards Date: Wed, 13 May 2015 08:13:47 -0600 Message-Id: <1431526427-13340-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Regenerate the pinmux from the latest tegra-pinmux-scripts. Signed-off-by: Simon Glass --- arch/arm/boot/dts/tegra124-nyan-big.dts | 22 +++++++++++----------- arch/arm/boot/dts/tegra124-nyan-blaze.dts | 30 +++++++++++++++--------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 2d21253..0eb2b0f 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -30,7 +30,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: common { + state_default: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = ; @@ -1098,19 +1098,19 @@ }; cam_i2c_scl_pbb1 { nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; cam_i2c_sda_pbb2 { nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; pbb3 { nvidia,pins = "pbb3"; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 0d30c51..1fc0da9 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -26,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; - pinmux_default: common { + state_default: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,pull = ; @@ -437,18 +437,18 @@ usb_vbus_en0_pn4 { nvidia,pins = "usb_vbus_en0_pn4"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; usb_vbus_en1_pn5 { nvidia,pins = "usb_vbus_en1_pn5"; nvidia,function = "usb"; - nvidia,pull = ; + nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,open-drain = ; }; hdmi_int_pn7 { nvidia,pins = "hdmi_int_pn7"; @@ -1094,19 +1094,19 @@ }; cam_i2c_scl_pbb1 { nvidia,pins = "cam_i2c_scl_pbb1"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; cam_i2c_sda_pbb2 { nvidia,pins = "cam_i2c_sda_pbb2"; - nvidia,function = "rsvd3"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,open-drain = ; + nvidia,function = "i2c3"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + nvidia,open-drain = ; }; pbb3 { nvidia,pins = "pbb3";