From patchwork Mon May 4 14:48:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 467621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5F6C6140295 for ; Tue, 5 May 2015 00:48:49 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=jQDuYHRY; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751057AbbEDOss (ORCPT ); Mon, 4 May 2015 10:48:48 -0400 Received: from mail-pa0-f47.google.com ([209.85.220.47]:36272 "EHLO mail-pa0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750942AbbEDOsr (ORCPT ); Mon, 4 May 2015 10:48:47 -0400 Received: by pabsx10 with SMTP id sx10so162585654pab.3 for ; Mon, 04 May 2015 07:48:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id; bh=tgVmyPALZMGIoN/ad1eeuq592yBCHq2Nx2UTOgN4s/8=; b=jQDuYHRY7tWoYNXUuTZrosKCQSv2dPULC+wtijBCfTjJcUw/7RG+V80yOXM3q1Tjo/ 8x4z+E5++sUenPi34kl2c5y/TXq3RTqrQfmCKVT9NIiEZIXFeDCXSzzkomTlSo/D5M46 gFcKjWlU1H1l9zHqJtLCZu4eKiyACIBkB4nNwCvmde5lKvt6aR0QvB1XTLgWPL+9Xnc4 8CcQmtDV9vHiqsduoI9sbjnFatA3GUkDibIig9EBfcEc7fSBBi3ReAnGU4jT5f6193ok xb2tlgl/RcbzNQ1yv2LGmHda4O4JXtz1a04wtgl1uRBVDnBExRsv4RDtJNhLbQWdtKVU Ye1g== X-Received: by 10.70.89.102 with SMTP id bn6mr43351274pdb.48.1430750927410; Mon, 04 May 2015 07:48:47 -0700 (PDT) Received: from localhost ([216.228.120.20]) by mx.google.com with ESMTPSA id jc6sm13061053pbd.4.2015.05.04.07.48.45 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 May 2015 07:48:46 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Stephen Warren , Alexandre Courbot , Peter De Schrijver , Paul Walmsley , linux-tegra@vger.kernel.org Subject: [PATCH 1/3] soc/tegra: fuse: Add spare bit offset for Tegra114 Date: Mon, 4 May 2015 16:48:41 +0200 Message-Id: <1430750923-23682-1-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.3.5 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding The offset of the first spare bit register on Tegra114 is 0x280. Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra30.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 5a6c533417fc..a55664fda81e 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -117,6 +117,7 @@ const struct tegra_fuse_soc tegra30_fuse_soc = { static const struct tegra_fuse_info tegra114_fuse_info = { .read = tegra30_fuse_read, .size = 0x2a0, + .spare = 0x280, }; const struct tegra_fuse_soc tegra114_fuse_soc = {