From patchwork Wed Apr 29 17:21:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rhyland Klein X-Patchwork-Id: 466196 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 87FAE1402BD for ; Thu, 30 Apr 2015 03:26:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423238AbbD2R0H (ORCPT ); Wed, 29 Apr 2015 13:26:07 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:11240 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S966536AbbD2RXB (ORCPT ); Wed, 29 Apr 2015 13:23:01 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Wed, 29 Apr 2015 10:22:22 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 29 Apr 2015 10:21:29 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 29 Apr 2015 10:21:29 -0700 Received: from rklein-work.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Wed, 29 Apr 2015 10:22:59 -0700 From: Rhyland Klein To: Peter De Schrijver CC: Mike Turquette , Stephen Warren , Stephen Boyd , Thierry Reding , Alexandre Courbot , linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Rhyland Klein , Bill Huang Subject: [PATCH v2 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Date: Wed, 29 Apr 2015 13:21:41 -0400 Message-ID: <1430328109-537-12-git-send-email-rklein@nvidia.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1430328109-537-1-git-send-email-rklein@nvidia.com> References: <1430328109-537-1-git-send-email-rklein@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Bill Huang If a PLL has a reset_reg specified, properly handle that in the enable/disable logic paths. Signed-off-by: Bill Huang --- v2: - Moved reset logic to _clk_pll_enable/disable as well drivers/clk/tegra/clk-pll.c | 12 ++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 14 insertions(+) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 0b9cbe12a3eb..3c40a8136136 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw) udelay(2); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val &= ~BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + clk_pll_enable_lock(pll); val = pll_readl_base(pll); @@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw) writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); } + if (pll->params->reset_reg) { + val = pll_readl(pll->params->reset_reg, pll); + val |= BIT(pll->params->reset_bit_idx); + pll_writel(val, pll->params->reset_reg, pll); + } + if (pll->params->iddq_reg) { val = pll_readl(pll->params->iddq_reg, pll); val |= BIT(pll->params->iddq_bit_idx); diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index b009c803f277..142999f1cd24 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -217,6 +217,8 @@ struct tegra_clk_pll_params { u32 lock_enable_bit_idx; u32 iddq_reg; u32 iddq_bit_idx; + u32 reset_reg; + u32 reset_bit_idx; u32 sdm_din_reg; u32 sdm_din_mask; u32 sdm_ctrl_reg;