From patchwork Thu Mar 12 12:15:14 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 449411 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9805C14010F for ; Thu, 12 Mar 2015 23:16:44 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932195AbbCLMQ2 (ORCPT ); Thu, 12 Mar 2015 08:16:28 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:6278 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932186AbbCLMQX (ORCPT ); Thu, 12 Mar 2015 08:16:23 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 12 Mar 2015 05:15:56 -0700 Received: from hqemhub02.nvidia.com ([172.20.150.31]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:14:15 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 12 Mar 2015 05:14:15 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:16:23 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:16:22 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com CC: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, Vince Hsu Subject: [PATCH v2 13/17] PCI: tegra: remove the power sequence from driver Date: Thu, 12 Mar 2015 20:15:14 +0800 Message-ID: <1426162518-7405-14-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org We have the generic PM domain support for Tegra SoCs now. So remove the duplicated power sequence here. Signed-off-by: Vince Hsu --- v2: enable pex clock when powering on drivers/pci/host/pci-tegra.c | 22 +++------------------- 1 file changed, 3 insertions(+), 19 deletions(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 00e92720d7f7..b1e2794d6dfa 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -931,12 +931,6 @@ static void tegra_pcie_power_off(struct tegra_pcie *pcie) if (err < 0) dev_warn(pcie->dev, "failed to power off PHY: %d\n", err); - reset_control_assert(pcie->pcie_xrst); - reset_control_assert(pcie->afi_rst); - reset_control_assert(pcie->pex_rst); - - tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); - err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies); if (err < 0) dev_warn(pcie->dev, "failed to disable regulators: %d\n", err); @@ -947,27 +941,17 @@ static int tegra_pcie_power_on(struct tegra_pcie *pcie) const struct tegra_pcie_soc_data *soc = pcie->soc_data; int err; - reset_control_assert(pcie->pcie_xrst); - reset_control_assert(pcie->afi_rst); - reset_control_assert(pcie->pex_rst); - - tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); - /* enable regulators */ err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies); if (err < 0) dev_err(pcie->dev, "failed to enable regulators: %d\n", err); - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE, - pcie->pex_clk, - pcie->pex_rst); - if (err) { - dev_err(pcie->dev, "powerup sequence failed: %d\n", err); + err = clk_prepare_enable(pcie->pex_clk); + if (err < 0) { + dev_err(pcie->dev, "failed to enable PEX clock: %d\n", err); return err; } - reset_control_deassert(pcie->afi_rst); - err = clk_prepare_enable(pcie->afi_clk); if (err < 0) { dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);