From patchwork Thu Feb 12 14:06:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 439199 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 51CB51400DE for ; Fri, 13 Feb 2015 01:11:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932368AbbBLOIu (ORCPT ); Thu, 12 Feb 2015 09:08:50 -0500 Received: from mail-wi0-f171.google.com ([209.85.212.171]:57582 "EHLO mail-wi0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932365AbbBLOIr (ORCPT ); Thu, 12 Feb 2015 09:08:47 -0500 Received: by mail-wi0-f171.google.com with SMTP id hi2so4525621wib.4; Thu, 12 Feb 2015 06:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oGPiw+wLKL/Ed0lbQO/cLbAtS95yslDxOuA6CPf/Bks=; b=ffDUwE/7NM5fyxy174ilqFDz83A5ESOdauVDUiBACs6HoBe+xN81fi8yZp84nN899s GwkEgamYUwaGp5EOXyktXZOLMj30iGtodphCT2S3t0KJOli8vnkJThHXROdOgZJ99FFf 2YM5bGQmHewxkEzivEON/pid6MTejp+o2WLYJ9CFSIeCqw96g1R1CWGjvEf400aHX36v 1tter2xlgjvA/DwBuUtr0VbRfx4nyBEzZEd4fM6/jN7JUtmWgi8m10O51ibMSqVJJYii yTcgC6STTUBAtX7PCW5lAwGlr5rUSzEXEBWy+W/oCfA7KkAHNtwzbbLJDUfFtwz3SadJ w5kQ== X-Received: by 10.180.12.233 with SMTP id b9mr6318720wic.49.1423750125340; Thu, 12 Feb 2015 06:08:45 -0800 (PST) Received: from cizrna.lan (37-48-47-45.tmcz.cz. [37.48.47.45]) by mx.google.com with ESMTPSA id df8sm2711911wib.2.2015.02.12.06.08.42 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Feb 2015 06:08:44 -0800 (PST) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Mikko Perttunen , Mikko Perttunen , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , Stephen Warren , Thierry Reding , Alexandre Courbot , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 08/15] ARM: tegra: Add EMC to Tegra124 device tree Date: Thu, 12 Feb 2015 15:06:24 +0100 Message-Id: <1423750042-6535-9-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1423750042-6535-1-git-send-email-tomeu.vizoso@collabora.com> References: <1423750042-6535-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen This adds a node for the EMC memory controller. It is always enabled, but only provides read-only functionality without board-specific timing tables. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso --- v5: Add a phandle to the CAR node that points to the EMC node --- arch/arm/boot/dts/tegra124.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4be06c6..0fff4fb 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -207,6 +207,7 @@ reg = <0x0 0x60006000 0x0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; + nvidia,external-memory-controller = <&emc>; }; flow-controller@0,60007000 { @@ -569,6 +570,13 @@ #iommu-cells = <1>; }; + emc: emc@0,7001b000 { + compatible = "nvidia,tegra124-emc"; + reg = <0x0 0x7001b000 0x0 0x1000>; + + nvidia,memory-controller = <&mc>; + }; + sata@0,70020000 { compatible = "nvidia,tegra124-ahci";