From patchwork Thu Feb 12 14:06:19 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 439210 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id CAC771400DE for ; Fri, 13 Feb 2015 01:14:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932313AbbBLOIV (ORCPT ); Thu, 12 Feb 2015 09:08:21 -0500 Received: from mail-we0-f170.google.com ([74.125.82.170]:37888 "EHLO mail-we0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932290AbbBLOIT (ORCPT ); Thu, 12 Feb 2015 09:08:19 -0500 Received: by mail-we0-f170.google.com with SMTP id q59so10353675wes.1; Thu, 12 Feb 2015 06:08:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=LtB5DDgtgPrAEq3Wx4z0h+8JM7TsJTAHjPR7rU6pe2o=; b=nDrKVlgO97xsXSdKXiPaR2sczS0iV/4gqz7bM/0aazHIna4qUwCV38oS59hQEsBCwq BvWrzVWnKbiQF73sp8KQ9b3M29951muPVObO7DbUJEjL45fOSI33Ry0KHlGIhxRdYfaj okuMmFQ3ht8pjKXep5na9Wcf/MCAS6bAUE0mfGNqXBFt9DAZLdCgGTIevF3rZNxnv5QW Uyk6rdbcG5MwumJxzHrJgrJlMmjcWIcCSjU5F6/PFuX7cqTu30CvQlwHc5fdWOedQFg9 YZAUzJ51oY89/AvK+A/Jx0VW719s3+vuIHg47aUksk0mL+wKzWCyjkRj9wTlerFoWbLK tsTw== X-Received: by 10.194.158.39 with SMTP id wr7mr8324163wjb.118.1423750097774; Thu, 12 Feb 2015 06:08:17 -0800 (PST) Received: from cizrna.lan (37-48-47-45.tmcz.cz. [37.48.47.45]) by mx.google.com with ESMTPSA id df8sm2711911wib.2.2015.02.12.06.08.15 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Feb 2015 06:08:16 -0800 (PST) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Mikko Perttunen , Mikko Perttunen , Tomeu Vizoso , Stephen Warren , Thierry Reding , Alexandre Courbot , Peter De Schrijver , linux-kernel@vger.kernel.org Subject: [PATCH v6 03/15] soc/tegra: Add ram code reader helper Date: Thu, 12 Feb 2015 15:06:19 +0100 Message-Id: <1423750042-6535-4-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1423750042-6535-1-git-send-email-tomeu.vizoso@collabora.com> References: <1423750042-6535-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Mikko Perttunen Needed for the EMC and MC drivers to know what timings from the DT to use. Signed-off-by: Mikko Perttunen Signed-off-by: Tomeu Vizoso --- v4: Replace magic number with PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +++++++++++++++++++ include/soc/tegra/fuse.h | 1 + 2 files changed, 20 insertions(+) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index 3bf5aba..dc96a62 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -28,8 +28,13 @@ #define APBMISC_SIZE 0x64 #define FUSE_SKU_INFO 0x10 +#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4 +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT) + static void __iomem *apbmisc_base; static void __iomem *strapping_base; +static bool long_ram_code; u32 tegra_read_chipid(void) { @@ -54,6 +59,18 @@ u32 tegra_read_straps(void) return 0; } +u32 tegra_read_ram_code(void) +{ + u32 straps = tegra_read_straps(); + + if (long_ram_code) + straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG; + else + straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT; + + return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT; +} + static const struct of_device_id apbmisc_match[] __initconst = { { .compatible = "nvidia,tegra20-apbmisc", }, {}, @@ -112,4 +129,6 @@ void __init tegra_init_apbmisc(void) strapping_base = of_iomap(np, 1); if (!strapping_base) pr_err("ioremap tegra strapping_base failed\n"); + + long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code"); } diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h index b5f7b5f..b019e34 100644 --- a/include/soc/tegra/fuse.h +++ b/include/soc/tegra/fuse.h @@ -56,6 +56,7 @@ struct tegra_sku_info { }; u32 tegra_read_straps(void); +u32 tegra_read_ram_code(void); u32 tegra_read_chipid(void); int tegra_fuse_readl(unsigned long offset, u32 *value);