From patchwork Wed Jan 14 06:19:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 428785 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E44EC140297 for ; Wed, 14 Jan 2015 17:19:35 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751581AbbANGTf (ORCPT ); Wed, 14 Jan 2015 01:19:35 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:8652 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751541AbbANGTf (ORCPT ); Wed, 14 Jan 2015 01:19:35 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 13 Jan 2015 22:19:54 -0800 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 13 Jan 2015 22:18:15 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 13 Jan 2015 22:18:15 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.342.0; Tue, 13 Jan 2015 22:19:34 -0800 Received: from vinceh-gnome.nvidia.com (Not Verified[10.19.108.119]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Tue, 13 Jan 2015 22:19:34 -0800 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com CC: linux-tegra@vger.kernel.org, Vince Hsu Subject: [RFC PATCH 5/9] ARM: tegra: add PM domain device nodes to Tegra124 DT Date: Wed, 14 Jan 2015 14:19:28 +0800 Message-ID: <1421216372-8025-6-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1421216372-8025-1-git-send-email-vinceh@nvidia.com> References: <1421216372-8025-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Also bind the PM domain provider and consumer together. Signed-off-by: Vince Hsu --- arch/arm/boot/dts/tegra124.dtsi | 73 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 72 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4be06c6ea0c8..584307b2953e 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,8 @@ 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + power-domains = <&pmc TEGRA_POWERGATE_PCIE>; + clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, <&tegra_car TEGRA124_CLK_PLL_E>, @@ -98,6 +101,7 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; + power-domains = <&pmc TEGRA_POWERGATE_DIS>; clocks = <&tegra_car TEGRA124_CLK_DISP1>, <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "dc", "parent"; @@ -187,6 +191,7 @@ clock-names = "gpu", "pwr"; resets = <&tegra_car 184>; reset-names = "gpu"; + power-domains = <&pmc TEGRA_POWERGATE_3D>; status = "disabled"; }; @@ -542,11 +547,75 @@ clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@0,7000e400 { + pmc: pmc@0,7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #power-domain-cells = <1>; + }; + + dc-power-domain { + compatible = "nvidia,power-domains"; + name = "dc-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + resets = <&tegra_car 27>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_DC>; + depend-on = <&sorpd>; + }; + + pcie-power-domain { + compatible = "nvidia,power-domains"; + name = "pcie-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_AFI>; + }; + + sorpd: sor-power-domain { + compatible = "nvidia,power-domains"; + name = "sor-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_MIPI_CAL>, + <&tegra_car TEGRA124_CLK_DPAUX>; + resets = <&tegra_car 182>, + <&tegra_car 48>, + <&tegra_car 82>, + <&tegra_car 51>, + <&tegra_car 56>; + }; + + gpu-power-domain { + compatible = "nvidia,power-domains"; + name = "gpu-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + resets = <&tegra_car 184>; + external-power-rail; + }; + + sata-power-domain { + compatible = "nvidia,power-domains"; + name = "sata-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>; + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; }; fuse@0,7000f800 { @@ -588,6 +657,8 @@ <&tegra_car 129>; reset-names = "sata", "sata-oob", "sata-cold"; + power-domains = <&pmc TEGRA_POWERGATE_SATA>; + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; phy-names = "sata-phy";