From patchwork Tue Dec 23 10:39:57 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 423651 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id D05E21400B7 for ; Tue, 23 Dec 2014 21:42:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755893AbaLWKkX (ORCPT ); Tue, 23 Dec 2014 05:40:23 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18021 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755869AbaLWKkS (ORCPT ); Tue, 23 Dec 2014 05:40:18 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 23 Dec 2014 02:40:20 -0800 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 23 Dec 2014 02:38:34 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 23 Dec 2014 02:38:34 -0800 Received: from vinceh-gnome.nvidia.com (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.342.0; Tue, 23 Dec 2014 02:40:17 -0800 From: Vince Hsu To: thierry.reding@gmail.com, swarren@wwwdotorg.org, gnurou@gmail.com, bskeggs@redhat.com, martin.peres@free.fr, seven@nimrod-online.com, samuel.pitoiset@gmail.com CC: nouveau@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Vince Hsu Subject: [PATCH 4/11] ARM: tegra: add mc node for Tegra124 GPU Date: Tue, 23 Dec 2014 18:39:57 +0800 Message-ID: <1419331204-26679-5-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1419331204-26679-1-git-send-email-vinceh@nvidia.com> References: <1419331204-26679-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra124 GPU needs the memory controller for the memory flush operatoin. So add the node reference of memory controller in device tree. Signed-off-by: Vince Hsu --- arch/arm/boot/dts/tegra124.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4be06c6ea0c8..4109c4548b55 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -187,6 +187,7 @@ clock-names = "gpu", "pwr"; resets = <&tegra_car 184>; reset-names = "gpu"; + mc = <&mc TEGRA_SWGROUP_GPU>; status = "disabled"; };