From patchwork Thu Dec 4 13:31:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 417779 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 78FE21400E2 for ; Fri, 5 Dec 2014 00:31:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751370AbaLDNbz (ORCPT ); Thu, 4 Dec 2014 08:31:55 -0500 Received: from mail-pa0-f73.google.com ([209.85.220.73]:61187 "EHLO mail-pa0-f73.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751322AbaLDNby (ORCPT ); Thu, 4 Dec 2014 08:31:54 -0500 Received: by mail-pa0-f73.google.com with SMTP id lj1so2392380pab.4 for ; Thu, 04 Dec 2014 05:31:53 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vEqUv6F1v455Mh3+c2UVmAoL5f9ghGCpmVhScH9cdZ8=; b=b3ZdHfulf4xdk8tSMhPjbjeVJKDIXoXna++7xNh9eM2VjUbGCONW3yPq42VJ4kcfUF ctGmFPRR4d5W8f/Gi2dxTux2ZWtS0Oc5KXJKitMVw/n5cplHN5jVDEkvjdwOdqji/Y61 y1ObxG2rCfW5exN8r9XjBl/XDBnYpq5Pq12LeiLvdZL1o61rNnyFDfnzGLzp8WJzAxG5 046LF0/ZjibCjT186h+62O2mQ7z0oTJDbW0VvyFfnhcFK0Px3P6itGaQ94rUmqoP8Htm OGM2GFrLkXBOD6XS/8hACs+iUmxnm3Y80tSG8mCZhceTMXsCa48IlM7aPHcVDUwp2Bwo Yaew== X-Gm-Message-State: ALoCoQmIQTIpfqxAmZX5+jKVMzreaew6rHxUaZGj1sjEXgGq+zI2wg2lQ2/n3/Fpsbu5OcPfug94 X-Received: by 10.66.229.42 with SMTP id sn10mr9501500pac.15.1417699913904; Thu, 04 Dec 2014 05:31:53 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id r6si1129443yhg.1.2014.12.04.05.31.53 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Dec 2014 05:31:53 -0800 (PST) Received: from kaki.bld.corp.google.com ([172.29.216.32]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id OhfcCakS.1; Thu, 04 Dec 2014 05:31:53 -0800 Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 1C105220615; Thu, 4 Dec 2014 06:31:52 -0700 (MST) From: Simon Glass To: linux-tegra@vger.kernel.org Cc: Stephen Warren , Simon Glass Subject: [PATCH v2] Add support for Nyan-big Date: Thu, 4 Dec 2014 06:31:51 -0700 Message-Id: <1417699911-17901-1-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 2.2.0.rc0.207.ga3a616c Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add support for Tegra124 Nyan-big. Pinmux is based on norrin with a single change for the reset GPIO. Signed-off-by: Simon Glass --- Changes in v2: - Rename from Nyan to Nyan-big configs/nyan-big.board | 198 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 configs/nyan-big.board diff --git a/configs/nyan-big.board b/configs/nyan-big.board new file mode 100644 index 0000000..7da5b4d --- /dev/null +++ b/configs/nyan-big.board @@ -0,0 +1,198 @@ +soc = 'tegra124' + +pins = ( + #pin, mux, gpio_init, pull, tri, e_inp, od, rcv_sel + ('dap_mclk1_pw4', 'extperiph1', None, 'none', False, False, False, False), + ('dap_mclk1_req_pee2', 'rsvd4', None, 'down', True, False, False, False), + ('dap1_din_pn1', 'rsvd4', None, 'down', True, False, False, False), + ('dap1_dout_pn2', 'i2s0', None, 'down', True, False, False, False), + ('dap1_fs_pn0', 'rsvd4', None, 'down', True, False, False, False), + ('dap1_sclk_pn3', 'rsvd4', None, 'down', True, False, False, False), + ('dap2_din_pa4', 'i2s1', None, 'none', False, True, False, False), + ('dap2_dout_pa5', 'i2s1', None, 'none', False, True, False, False), + ('dap2_fs_pa2', 'i2s1', None, 'none', False, True, False, False), + ('dap2_sclk_pa3', 'i2s1', None, 'none', False, True, False, False), + ('gpio_x4_aud_px4', None, 'in', 'none', False, True, False, False), + ('gpio_x5_aud_px5', 'rsvd4', None, 'down', True, False, False, False), + ('gpio_x6_aud_px6', 'gmi', None, 'down', True, False, False, False), + ('gpio_x7_aud_px7', None, 'out0', 'none', False, False, False, False), + ('gpio_w2_aud_pw2', 'rsvd2', None, 'down', True, False, False, False), + ('gpio_w3_aud_pw3', None, 'in', 'none', False, True, False, False), + ('dvfs_pwm_px0', 'cldvfs', None, 'none', False, False, False, False), + ('gpio_x1_aud_px1', None, 'in', 'none', False, True, False, False), + ('dvfs_clk_px2', 'cldvfs', None, 'none', False, False, False, False), + ('gpio_x3_aud_px3', 'rsvd4', None, 'down', True, False, False, False), + ('dap3_din_pp1', 'i2s2', None, 'down', True, False, False, False), + ('dap3_dout_pp2', None, 'out0', 'none', False, False, False, False), + ('dap3_fs_pp0', 'i2s2', None, 'down', True, False, False, False), + ('dap3_sclk_pp3', 'rsvd3', None, 'down', True, False, False, False), + ('pv0', None, 'in', 'none', False, True, False, False), + ('pv1', 'rsvd1', None, 'down', True, False, False, False), + ('ulpi_clk_py0', 'spi1', None, 'none', False, False, False, False), + ('ulpi_data0_po1', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data1_po2', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data2_po3', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data3_po4', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data4_po5', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data5_po6', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data6_po7', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_data7_po0', 'ulpi', None, 'down', True, False, False, False), + ('ulpi_dir_py1', 'spi1', None, 'none', False, True, False, False), + ('ulpi_nxt_py2', 'spi1', None, 'none', False, False, False, False), + ('ulpi_stp_py3', 'spi1', None, 'none', False, False, False, False), + ('cam_i2c_scl_pbb1', 'rsvd3', None, 'down', True, False, False, False), + ('cam_i2c_sda_pbb2', 'rsvd3', None, 'down', True, False, False, False), + ('cam_mclk_pcc0', 'vi', None, 'down', True, False, False, False), + ('pbb0', 'vgp6', None, 'down', True, False, False, False), + ('pbb3', 'vgp3', None, 'down', True, False, False, False), + ('pbb4', 'vgp4', None, 'down', True, False, False, False), + ('pbb5', 'rsvd3', None, 'down', True, False, False, False), + ('pbb6', 'rsvd2', None, 'down', True, False, False, False), + ('pbb7', 'rsvd2', None, 'down', True, False, False, False), + ('pcc1', 'rsvd2', None, 'down', True, False, False, False), + ('pcc2', 'rsvd2', None, 'down', True, False, False, False), + ('gen2_i2c_scl_pt5', 'i2c2', None, 'none', False, True, True, False), + ('gen2_i2c_sda_pt6', 'i2c2', None, 'none', False, True, True, False), + ('pj7', None, 'in', 'none', False, True, False, False), + ('pb0', 'rsvd2', None, 'down', True, False, False, False), + ('pb1', 'rsvd2', None, 'down', True, False, False, False), + ('pk7', None, 'in', 'none', False, True, False, False), + ('pg0', None, 'in', 'none', False, True, False, False), + ('pg1', None, 'in', 'none', False, True, False, False), + ('ph2', None, 'in', 'none', False, True, False, False), + ('ph3', 'gmi', None, 'down', True, False, False, False), + ('ph4', None, 'in', 'none', False, True, False, False), + ('ph5', 'rsvd2', None, 'down', True, False, False, False), + ('ph6', None, 'in', 'none', False, True, False, False), + ('ph7', None, 'out1', 'none', False, False, False, False), + ('pg2', None, 'in', 'none', False, True, False, False), + ('pg3', None, 'in', 'none', False, True, False, False), + ('pg4', 'spi4', None, 'none', False, False, False, False), + ('pg5', 'spi4', None, 'none', False, False, False, False), + ('pg6', 'spi4', None, 'none', False, False, False, False), + ('pg7', 'spi4', None, 'none', False, True, False, False), + ('ph0', 'gmi', None, 'down', True, False, False, False), + ('ph1', 'pwm1', None, 'none', False, False, False, False), + ('pk0', 'rsvd1', None, 'down', True, False, False, False), + ('pk1', None, 'out0', 'none', False, False, False, False), + ('pj0', None, 'in', 'up', False, True, False, False), + ('pj2', 'rsvd1', None, 'down', True, False, False, False), + ('pk3', 'gmi', None, 'down', True, False, False, False), + ('pk4', None, 'out0', 'up', False, False, False, False), + ('pk2', None, 'in', 'none', False, True, False, False), + ('pi3', 'spi4', None, 'none', False, False, False, False), + ('pi6', None, 'in', 'none', False, True, False, False), + ('pi2', 'rsvd4', None, 'down', True, False, False, False), + ('pi5', None, 'out1', 'up', False, False, False, False), + ('pi1', None, 'in', 'none', False, True, False, False), + ('pi4', 'gmi', None, 'down', True, False, False, False), + ('pi7', None, 'in', 'none', False, True, False, False), + ('pc7', None, 'in', 'none', False, True, False, False), + ('pi0', None, 'in', 'none', False, True, False, False), + ('pex_l0_clkreq_n_pdd2', 'rsvd2', None, 'down', True, False, False, False), + ('pex_l0_rst_n_pdd1', 'rsvd2', None, 'down', True, False, False, False), + ('pex_l1_clkreq_n_pdd6', 'rsvd2', None, 'down', True, False, False, False), + ('pex_l1_rst_n_pdd5', 'rsvd2', None, 'down', True, False, False, False), + ('pex_wake_n_pdd3', 'rsvd2', None, 'down', True, False, False, False), + ('usb_vbus_en2_pff1', 'rsvd2', None, 'down', True, False, False, False), + ('pff2', 'rsvd2', None, 'down', True, False, False, False), + ('clk2_out_pw5', 'rsvd2', None, 'down', True, False, False, False), + ('clk2_req_pcc5', 'rsvd2', None, 'down', True, False, False, False), + ('sdmmc1_wp_n_pv3', 'sdmmc1', None, 'down', True, False, False, False), + ('sdmmc1_clk_pz0', 'sdmmc1', None, 'none', False, True, False, False), + ('sdmmc1_cmd_pz1', 'sdmmc1', None, 'up', False, True, False, False), + ('sdmmc1_dat0_py7', 'sdmmc1', None, 'up', False, True, False, False), + ('sdmmc1_dat1_py6', 'sdmmc1', None, 'up', False, True, False, False), + ('sdmmc1_dat2_py5', 'sdmmc1', None, 'up', False, True, False, False), + ('sdmmc1_dat3_py4', 'sdmmc1', None, 'up', False, True, False, False), + ('sdmmc3_clk_pa6', 'sdmmc3', None, 'none', False, False, False, False), + ('sdmmc3_cmd_pa7', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc3_dat0_pb7', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc3_dat1_pb6', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc3_dat2_pb5', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc3_dat3_pb4', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc3_clk_lb_out_pee4', 'sdmmc3', None, 'none', False, False, False, False), + ('sdmmc3_clk_lb_in_pee5', 'sdmmc3', None, 'up', False, True, False, False), + ('sdmmc4_clk_pcc4', 'sdmmc4', None, 'none', False, True, False, False), + ('sdmmc4_cmd_pt7', 'sdmmc4', None, 'none', False, True, False, False), + ('sdmmc4_dat0_paa0', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat1_paa1', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat2_paa2', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat3_paa3', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat4_paa4', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat5_paa5', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat6_paa6', 'sdmmc4', None, 'up', False, True, False, False), + ('sdmmc4_dat7_paa7', 'sdmmc4', None, 'up', False, True, False, False), + ('kb_col0_pq0', None, 'in', 'none', False, True, False, False), + ('kb_col1_pq1', 'rsvd2', None, 'down', True, False, False, False), + ('kb_col2_pq2', None, 'in', 'none', False, True, False, False), + ('kb_col3_pq3', None, 'in', 'none', False, True, False, False), + ('kb_col4_pq4', 'sdmmc3', None, 'up', False, True, False, False), + ('kb_col5_pq5', 'rsvd2', None, 'down', True, False, False, False), + ('kb_col6_pq6', None, 'in', 'none', False, True, False, False), + ('kb_col7_pq7', None, 'in', 'none', False, True, False, False), + ('kb_row0_pr0', None, 'out0', 'none', False, False, False, False), + ('kb_row1_pr1', None, 'in', 'none', False, True, False, False), + ('kb_row10_ps2', 'uarta', None, 'none', False, True, False, False), + ('kb_row11_ps3', None, 'out0', 'none', False, False, False, False), + ('kb_row12_ps4', None, 'out0', 'none', False, False, False, False), + ('kb_row13_ps5', 'rsvd2', None, 'down', True, False, False, False), + ('kb_row14_ps6', 'rsvd2', None, 'down', True, False, False, False), + ('kb_row15_ps7', None, 'in', 'none', False, True, False, False), + ('kb_row16_pt0', 'rsvd2', None, 'down', True, False, False, False), + ('kb_row17_pt1', None, 'in', 'none', False, True, False, False), + ('kb_row2_pr2', 'rsvd2', None, 'down', True, False, False, False), + ('kb_row3_pr3', 'kbc', None, 'down', True, False, False, False), + ('kb_row4_pr4', None, 'in', 'none', False, True, False, False), + ('kb_row5_pr5', 'rsvd3', None, 'down', True, False, False, False), + ('kb_row6_pr6', 'kbc', None, 'down', True, False, False, False), + ('kb_row7_pr7', None, 'in', 'none', False, True, False, False), + ('kb_row8_ps0', 'rsvd2', None, 'down', True, False, False, False), + ('kb_row9_ps1', 'uarta', None, 'down', False, False, False, False), + ('sdmmc3_cd_n_pv2', 'sdmmc3', None, 'up', False, True, False, False), + ('clk_32k_out_pa0', None, 'in', 'none', False, True, False, False), + ('pwr_i2c_scl_pz6', 'i2cpwr', None, 'none', False, True, True, False), + ('pwr_i2c_sda_pz7', 'i2cpwr', None, 'none', False, True, True, False), + ('jtag_rtck', 'rtck', None, 'none', False, False, False, False), + ('clk_32k_in', 'clk', None, 'none', False, True, False, False), + ('core_pwr_req', 'pwron', None, 'none', False, False, False, False), + ('cpu_pwr_req', 'cpu', None, 'none', False, False, False, False), + ('pwr_int_n', 'pmi', None, 'none', False, True, False, False), + ('reset_out_n', 'reset_out_n', None, 'none', False, False, False, False), + ('clk3_out_pee0', 'rsvd2', None, 'down', True, False, False, False), + ('clk3_req_pee1', 'rsvd2', None, 'down', True, False, False, False), + ('dap4_din_pp5', 'rsvd3', None, 'down', True, False, False, False), + ('dap4_dout_pp6', 'rsvd4', None, 'down', True, False, False, False), + ('dap4_fs_pp4', 'rsvd4', None, 'down', True, False, False, False), + ('dap4_sclk_pp7', 'rsvd3', None, 'down', True, False, False, False), + ('gen1_i2c_scl_pc4', 'i2c1', None, 'none', False, True, True, False), + ('gen1_i2c_sda_pc5', 'i2c1', None, 'none', False, True, True, False), + ('pu0', 'rsvd4', None, 'down', True, False, False, False), + ('pu1', 'rsvd1', None, 'down', True, False, False, False), + ('pu2', 'rsvd1', None, 'down', True, False, False, False), + ('pu3', 'gmi', None, 'down', True, False, False, False), + ('pu4', None, 'in', 'none', False, True, False, False), + ('pu5', None, 'in', 'up', False, True, False, False), + ('pu6', None, 'in', 'up', False, True, False, False), + ('uart2_cts_n_pj5', 'gmi', None, 'down', True, False, False, False), + ('uart2_rts_n_pj6', 'gmi', None, 'down', True, False, False, False), + ('uart2_rxd_pc3', 'irda', None, 'down', True, False, False, False), + ('uart2_txd_pc2', 'irda', None, 'down', True, False, False, False), + ('uart3_cts_n_pa1', 'gmi', None, 'down', True, False, False, False), + ('uart3_rts_n_pc0', 'gmi', None, 'down', True, False, False, False), + ('uart3_rxd_pw7', 'rsvd2', None, 'down', True, False, False, False), + ('uart3_txd_pw6', 'rsvd2', None, 'down', True, False, False, False), + ('owr', 'rsvd2', None, 'down', True, False, False, False), + ('hdmi_cec_pee3', 'cec', None, 'none', False, True, True, False), + ('hdmi_int_pn7', None, 'in', 'down', False, True, False, False), + ('ddc_scl_pv4', 'i2c4', None, 'none', False, True, False, False), + ('ddc_sda_pv5', 'i2c4', None, 'none', False, True, False, False), + ('spdif_out_pk5', 'rsvd2', None, 'down', True, False, False, False), + ('spdif_in_pk6', None, 'out0', 'down', False, False, False, False), + ('usb_vbus_en0_pn4', 'usb', None, 'none', False, True, True, False), + ('usb_vbus_en1_pn5', 'usb', None, 'none', False, True, True, False), + ('dp_hpd_pff0', 'dp', None, 'up', False, True, False, False), +) + +drive_groups = ( +)