From patchwork Tue Nov 25 00:17:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Bresticker X-Patchwork-Id: 414184 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A33FF140187 for ; Tue, 25 Nov 2014 11:19:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751650AbaKYASK (ORCPT ); Mon, 24 Nov 2014 19:18:10 -0500 Received: from mail-oi0-f74.google.com ([209.85.218.74]:50571 "EHLO mail-oi0-f74.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751636AbaKYARo (ORCPT ); Mon, 24 Nov 2014 19:17:44 -0500 Received: by mail-oi0-f74.google.com with SMTP id e131so1266866oig.1 for ; Mon, 24 Nov 2014 16:17:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VXKkMYSIgRVEBIwoJuOhPbQUqe9NbcKJYhmrpA0Rz8U=; b=lyubJu+i8TYLASVfa9OLKO80u5vIIAbgWiDd8zXUqhbdWht+F19/wPz4w+CC+5CfwV VO8RlAy9lT90n19Zor9KL64i7I1LuoZYl82azQx2VjGABAreQR3O8WFrOm9kakPycIFc 1JPWj3zztArYQ68Lh0ACztfCopDHNr3gChvYpibqDnPp6OJlSC1e/vxLSI4yJELg8Ea1 UfH8Azimj3N0vz1B3RyKh/Dr+jeC5psbKvRw3QsDx4a0V5ZWqL1JMUGJW1Rp2fOAjw3Y ht7rxan3ST5V2v1wuiTWl1B2HxXhQ+ei+MGpK1m/skWKZWd65aNFmyGON7R6J3cmDBhl O6zw== X-Gm-Message-State: ALoCoQmSJwJo+2xBYE0vEltAoWLrleF5FByWkSY/cOfdgCmiY8crPvnPXqvVBvbQyN4QkOV/ufIb X-Received: by 10.42.86.193 with SMTP id v1mr1699143icl.10.1416874663742; Mon, 24 Nov 2014 16:17:43 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id s23si514765yhf.0.2014.11.24.16.17.42 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 24 Nov 2014 16:17:43 -0800 (PST) Received: from abrestic.mtv.corp.google.com ([172.22.65.70]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id 1UwEyHi2.2; Mon, 24 Nov 2014 16:17:43 -0800 Received: by abrestic.mtv.corp.google.com (Postfix, from userid 137652) id B838C2213BF; Mon, 24 Nov 2014 16:17:41 -0800 (PST) From: Andrew Bresticker To: Stephen Warren , Thierry Reding , Alexandre Courbot , linux-tegra@vger.kernel.org Cc: Andrew Bresticker , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Jassi Brar , Linus Walleij , Greg Kroah-Hartman , Mathias Nyman , Grant Likely , Alan Stern , Arnd Bergmann , Olof Johansson , Kishon Vijay Abraham I , Felipe Balbi , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-usb@vger.kernel.org Subject: [PATCH V6 11/12] ARM: tegra: Add Tegra124 XUSB mailbox and xHCI controller Date: Mon, 24 Nov 2014 16:17:23 -0800 Message-Id: <1416874644-12070-12-git-send-email-abrestic@chromium.org> X-Mailer: git-send-email 2.1.0.rc2.206.gedb03e5 In-Reply-To: <1416874644-12070-1-git-send-email-abrestic@chromium.org> References: <1416874644-12070-1-git-send-email-abrestic@chromium.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add nodes for the Tegra XUSB mailbox and Tegra xHCI controller and add the PHY mailbox channel to the XUSB padctl node. Signed-off-by: Andrew Bresticker Reviewed-by: Stephen Warren --- No changes from v3/v4/v5. Changes from v2: - Dropped channel specifier from mailbox bindings. - Added mbox-names properties. Changes from v1: - Updated to use common mailbox bindings. - Added remaining clocks/resets. --- arch/arm/boot/dts/tegra124.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index df2b06b..2e06130 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -591,11 +591,52 @@ status = "disabled"; }; + usb@0,70090000 { + compatible = "nvidia,tegra124-xhci"; + reg = <0x0 0x70090000 0x0 0x8000>, + <0x0 0x70098000 0x0 0x1000>, + <0x0 0x70099000 0x0 0x1000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, + <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_DEV>, + <&tegra_car TEGRA124_CLK_XUSB_DEV_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_SS>, + <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, + <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, + <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, + <&tegra_car TEGRA124_CLK_PLL_U_480M>, + <&tegra_car TEGRA124_CLK_CLK_M>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "xusb_host", "xusb_host_src", "xusb_dev", + "xusb_dev_src", "xusb_falcon_src", "xusb_ss", + "xusb_ss_div2", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; + resets = <&tegra_car 89>, <&tegra_car 95>, <&tegra_car 156>, + <&tegra_car 143>; + reset-names = "xusb_host", "xusb_dev", "xusb_ss", "xusb"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; + status = "disabled"; + }; + + xusb_mbox: mailbox@0,70098000 { + compatible = "nvidia,tegra124-xusb-mbox"; + reg = <0x0 0x70098000 0x0 0x1000>; + interrupts = ; + + #mbox-cells = <0>; + }; + padctl: padctl@0,7009f000 { compatible = "nvidia,tegra124-xusb-padctl"; reg = <0x0 0x7009f000 0x0 0x1000>; resets = <&tegra_car 142>; reset-names = "padctl"; + mboxes = <&xusb_mbox>; + mbox-names = "xusb"; #phy-cells = <1>; };