From patchwork Wed Oct 29 16:22:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomeu Vizoso X-Patchwork-Id: 404712 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 352A214008E for ; Thu, 30 Oct 2014 03:28:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934559AbaJ2Q1w (ORCPT ); Wed, 29 Oct 2014 12:27:52 -0400 Received: from mail-wg0-f52.google.com ([74.125.82.52]:33510 "EHLO mail-wg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934176AbaJ2QYI (ORCPT ); Wed, 29 Oct 2014 12:24:08 -0400 Received: by mail-wg0-f52.google.com with SMTP id b13so1709254wgh.11 for ; Wed, 29 Oct 2014 09:24:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=gKNLH3o67JR4rdNCn/0JDfzRXSE7O3snzIBWuQMbHsg=; b=oBU9blGB4EFnyEX3dsdGPC2IAddX+7G9YjOzJdzxwl+llH/8rs+8Y0rsw9Xn4Vzrvl uo8bM0D8gNe91hNeAj5TIdetwnuUFM5GhYXpcREkuNp1zmfucEPPOcW2ByYDCDYwe2gB 3TM9v6f29t7QWLVBi8X3LQZ4m4dokyyRXYjVV50BL6D9pJi7E7Vzv8NZMlhDo5YlSoOO 6FXuBJyN5JBIfA4VLbxzB4RvF4ruibmgrHS7FArPv1l2j4A40CKCa/iIi0l+2C0Mzgs+ GDdrjGUx/fIhIgspwcfGII59BL1SJD/wevZvWS/++L1zkxu1aECIoHMKeV2PHN4Yr60q kGEw== X-Received: by 10.194.71.84 with SMTP id s20mr3815557wju.128.1414599846814; Wed, 29 Oct 2014 09:24:06 -0700 (PDT) Received: from cizrna.lan (37-48-36-243.tmcz.cz. [37.48.36.243]) by mx.google.com with ESMTPSA id u2sm5699502wjz.11.2014.10.29.09.24.03 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 29 Oct 2014 09:24:05 -0700 (PDT) From: Tomeu Vizoso To: linux-tegra@vger.kernel.org Cc: Javier Martinez Canillas , Tomeu Vizoso , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Stephen Warren , Thierry Reding , Alexandre Courbot , Peter De Schrijver , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 02/13] of: Document long-ram-code property in nvidia, tegra20-apbmisc Date: Wed, 29 Oct 2014 17:22:20 +0100 Message-Id: <1414599796-30597-3-git-send-email-tomeu.vizoso@collabora.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1414599796-30597-1-git-send-email-tomeu.vizoso@collabora.com> References: <1414599796-30597-1-git-send-email-tomeu.vizoso@collabora.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Needed to properly decode the ram code register. Signed-off-by: Tomeu Vizoso --- v3: * Clarify wording as suggested by Mikko --- Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt index b97b8be..d034ff8 100644 --- a/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt +++ b/Documentation/devicetree/bindings/misc/nvidia,tegra20-apbmisc.txt @@ -11,3 +11,5 @@ Required properties: The second entry gives the physical address and length of the registers indicating the strapping options. +Optional properties: +- nvidia,long-ram-code: If present, the RAM code is long (4 bit). If not, short (2 bit).