From patchwork Mon Oct 13 10:21:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 399119 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4A7B4140076 for ; Mon, 13 Oct 2014 21:22:09 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753609AbaJMKWI (ORCPT ); Mon, 13 Oct 2014 06:22:08 -0400 Received: from mail-wg0-f52.google.com ([74.125.82.52]:43874 "EHLO mail-wg0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753601AbaJMKWI (ORCPT ); Mon, 13 Oct 2014 06:22:08 -0400 Received: by mail-wg0-f52.google.com with SMTP id a1so8239482wgh.35 for ; Mon, 13 Oct 2014 03:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cUFOaCoWEfu9938jZRmdCXEF2T+4dAkhoChNhBOZAKk=; b=e2M9AM6gzpngTBc+B9kMCXEq/SURooNLFzf9yH+sOktCPea+BJKpjq3O2ixxuaqbrg kPD/ZILJanz/i3e0K+9C/baQvKUP/mUwEfZROT/Edu9RjT1g4kdVrLyI38rnC8XeM7lC oNb44njSWb+mYj9VlNTW5ipDvQCBhOCZ7CGxxS5dJxeywfw9RuJRKt0U7vtYJNNNbbVC dDNl2AC707ygrVV28/Arp+NKffnc1+r5XVac3VOUtJogp4kvJrAOUcu5bdC1t14N1zxw 3ptVmyNtTDAJFZgSnCAnJnWTDaFVbt86AVknZkn5gOAUcbIft89iUvNR7rOjkKbfUubX KsLw== X-Received: by 10.180.101.134 with SMTP id fg6mr19892566wib.9.1413195726748; Mon, 13 Oct 2014 03:22:06 -0700 (PDT) Received: from localhost (port-4359.pppoe.wtnet.de. [84.46.17.24]) by mx.google.com with ESMTPSA id bc5sm14168505wjb.14.2014.10.13.03.22.05 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Oct 2014 03:22:06 -0700 (PDT) From: Thierry Reding To: dri-devel@lists.freedesktop.org Cc: Sean Paul , linux-tegra@vger.kernel.org Subject: [PATCH 07/14] gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL Date: Mon, 13 Oct 2014 12:21:48 +0200 Message-Id: <1413195715-4719-7-git-send-email-thierry.reding@gmail.com> X-Mailer: git-send-email 2.1.2 In-Reply-To: <1413195715-4719-1-git-send-email-thierry.reding@gmail.com> References: <1413195715-4719-1-git-send-email-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Sean Paul By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE ("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states that if the value of the prescale is 0 (or 0.1us), the filter should be set between 2-5. However, the current code sets it to 0. For now, let's keep the prescale and filter values as-is, which is most likely the power-on-reset values of 0x2 and 0xa, respectively. Signed-off-by: Sean Paul Signed-off-by: Thierry Reding --- drivers/gpu/host1x/mipi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/host1x/mipi.c b/drivers/gpu/host1x/mipi.c index a3e215a0116f..0d8c3ae8db6a 100644 --- a/drivers/gpu/host1x/mipi.c +++ b/drivers/gpu/host1x/mipi.c @@ -208,7 +208,9 @@ int tegra_mipi_calibrate(struct tegra_mipi_device *device) tegra_mipi_writel(device->mipi, value, modules[i].reg); } - tegra_mipi_writel(device->mipi, MIPI_CAL_CTRL_START, MIPI_CAL_CTRL); + value = tegra_mipi_readl(device->mipi, MIPI_CAL_CTRL); + value |= MIPI_CAL_CTRL_START; + tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL); err = tegra_mipi_wait(device->mipi);