From patchwork Thu Jul 10 21:42:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tuomas Tynkkynen X-Patchwork-Id: 368803 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8BA1414011B for ; Fri, 11 Jul 2014 07:44:53 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753214AbaGJVoY (ORCPT ); Thu, 10 Jul 2014 17:44:24 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:13333 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753113AbaGJVoA (ORCPT ); Thu, 10 Jul 2014 17:44:00 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Thu, 10 Jul 2014 14:44:50 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 10 Jul 2014 14:36:54 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 10 Jul 2014 14:36:54 -0700 Received: from ttynkkynen-lnx.Nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.342.0; Thu, 10 Jul 2014 14:43:59 -0700 From: Tuomas Tynkkynen To: , , , CC: Stephen Warren , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , Viresh Kumar , , Tuomas Tynkkynen Subject: [PATCH 13/13] ARM: tegra: Add entries for cpufreq on Tegra124 Date: Fri, 11 Jul 2014 00:42:49 +0300 Message-ID: <1405028569-14253-14-git-send-email-ttynkkynen@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> References: <1405028569-14253-1-git-send-email-ttynkkynen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen --- arch/arm/boot/dts/tegra124.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 582a0e2..5e290bf 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -776,6 +776,13 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; + + clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, + <&tegra_car TEGRA124_CLK_CCLK_LP>, + <&tegra_car TEGRA124_CLK_PLL_X>, + <&tegra_car TEGRA124_CLK_PLL_P>, + <&dfll>; + clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; }; cpu@1 {