From patchwork Fri Nov 16 23:20:31 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Dietrich X-Patchwork-Id: 199805 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 8E5A82C0082 for ; Sat, 17 Nov 2012 10:21:18 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753666Ab2KPXVR (ORCPT ); Fri, 16 Nov 2012 18:21:17 -0500 Received: from mailout-de.gmx.net ([213.165.64.22]:60292 "HELO mailout-de.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with SMTP id S1753653Ab2KPXVQ (ORCPT ); Fri, 16 Nov 2012 18:21:16 -0500 Received: (qmail invoked by alias); 16 Nov 2012 23:21:15 -0000 Received: from pD9E5C9D8.dip0.t-ipconnect.de (EHLO ax5200p.fritz.box) [217.229.201.216] by mail.gmx.net (mp028) with SMTP; 17 Nov 2012 00:21:15 +0100 X-Authenticated: #9962044 X-Provags-ID: V01U2FsdGVkX1/W/y4nhtnWfyo0GeQV/oVwW4xCpYyDWCPQMp0CQk ibw+EuNkU28DAL From: Marc Dietrich To: linux-tegra@vger.kernel.org Cc: Stephen Warren Subject: [PATCH v4 1/2] ARM: tegra: paz00: Add host1x support Date: Sat, 17 Nov 2012 00:20:31 +0100 Message-Id: <138e6f406aef20f6257a8f90af45865bd9c88092.1353107865.git.marvin24@gmx.de> X-Mailer: git-send-email 1.7.9.5 X-Y-GMX-Trusted: 0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This adds host1x support which includes LVDS support. HDMI is disabled for now as the tegra drm cannot handle two different display timings at the same time. Signed-off-by: Marc Dietrich --- V4: rebase against for-3.8/DT V3: move host1x up, revert hdmi ddc clock change arch/arm/boot/dts/tegra20-paz00.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 6a93d14..8a14e1d 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -10,6 +10,15 @@ reg = <0x00000000 0x20000000>; }; + host1x { + dc@54200000 { + rgb { + status = "okay"; + nvidia,ddc-i2c-bus = <&lvds_ddc>; + }; + }; + }; + pinmux { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -240,7 +249,7 @@ clock-frequency = <216000000>; }; - i2c@7000c000 { + lvds_ddc: i2c@7000c000 { status = "okay"; clock-frequency = <400000>;