| Message ID | 1384815306-3149-1-git-send-email-ebrower@nvidia.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Thierry Reding |
| Headers | show |
On Mon, Nov 18, 2013 at 02:55:06PM -0800, Eric Brower wrote: > Tegra20 and Tegra30 do not support gen2 PCIe, so correct the > register setting to disable it. > > Signed-off-by: Eric Brower <ebrower@nvidia.com> > --- > drivers/pci/host/pci-tegra.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c > index 0afbbbc..b8ba2f7 100644 > --- a/drivers/pci/host/pci-tegra.c > +++ b/drivers/pci/host/pci-tegra.c > @@ -805,7 +805,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) > afi_writel(pcie, value, AFI_PCIE_CONFIG); > > value = afi_readl(pcie, AFI_FUSE); > - value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; > + value |= AFI_FUSE_PCIE_T0_GEN2_DIS; > afi_writel(pcie, value, AFI_FUSE); > > /* initialize internal PHY, enable up to 16 PCIE lanes */ Bjorn: can you pick this up directly or would you rather have me prepare a branch? It's the only one for Tegra so far, so a branch wouldn't be all that useful. In case you want to pick it up directly: Acked-by: Thierry Reding <treding@nvidia.com>
On Mon, Nov 18, 2013 at 02:55:06PM -0800, Eric Brower wrote: > Tegra20 and Tegra30 do not support gen2 PCIe, so correct the > register setting to disable it. > > Signed-off-by: Eric Brower <ebrower@nvidia.com> Applied with Thierry's ack to pci/host-tegra for v3.14, thanks! Bjorn > --- > drivers/pci/host/pci-tegra.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c > index 0afbbbc..b8ba2f7 100644 > --- a/drivers/pci/host/pci-tegra.c > +++ b/drivers/pci/host/pci-tegra.c > @@ -805,7 +805,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) > afi_writel(pcie, value, AFI_PCIE_CONFIG); > > value = afi_readl(pcie, AFI_FUSE); > - value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; > + value |= AFI_FUSE_PCIE_T0_GEN2_DIS; > afi_writel(pcie, value, AFI_FUSE); > > /* initialize internal PHY, enable up to 16 PCIE lanes */ > -- > 1.8.1.5 > -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 0afbbbc..b8ba2f7 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -805,7 +805,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_PCIE_CONFIG); value = afi_readl(pcie, AFI_FUSE); - value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; + value |= AFI_FUSE_PCIE_T0_GEN2_DIS; afi_writel(pcie, value, AFI_FUSE); /* initialize internal PHY, enable up to 16 PCIE lanes */
Tegra20 and Tegra30 do not support gen2 PCIe, so correct the register setting to disable it. Signed-off-by: Eric Brower <ebrower@nvidia.com> --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)