diff mbox

[1/4] clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops

Message ID 1381220587-29697-2-git-send-email-josephl@nvidia.com
State Not Applicable, archived
Headers show

Commit Message

Joseph Lo Oct. 8, 2013, 8:23 a.m. UTC
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.

Cc: Mike Turquette <mturquette@linaro.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
This patch depends on the patch series "[PATCH 0/5] Tegra124 clock support"
that sent by Peter on 10/4/2013.
---
 drivers/clk/tegra/clk-tegra124.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

Comments

Stephen Warren Oct. 8, 2013, 4:51 p.m. UTC | #1
On 10/08/2013 02:23 AM, Joseph Lo wrote:
> Hook the functions for CPU hotplug support. After the CPU is hot
> unplugged, the flow controller will handle to clock gate the CPU clock.
> But still need to implement an empty function to avoid warning message.
> 
> Cc: Mike Turquette <mturquette@linaro.org>
> Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Joseph Lo <josephl@nvidia.com>
> ---
> This patch depends on the patch series "[PATCH 0/5] Tegra124 clock support"
> that sent by Peter on 10/4/2013.

Uggh. This series mixes patches for drivers/clk and arch/arm/mach-tegra.
I don't want to introduce dependencies between those two subsystems.
Instead, if this patch is applied to the clock tree, and the reset of
the patches to the Tegra tree, will that cause any build issues, or any
run-time for any SoC other than Tegra124 (which is a new feature so it's
fine if it doesn't work until everything is merged together)?
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Joseph Lo Oct. 9, 2013, 2:59 a.m. UTC | #2
On Wed, 2013-10-09 at 00:51 +0800, Stephen Warren wrote:
> On 10/08/2013 02:23 AM, Joseph Lo wrote:
> > Hook the functions for CPU hotplug support. After the CPU is hot
> > unplugged, the flow controller will handle to clock gate the CPU clock.
> > But still need to implement an empty function to avoid warning message.
> > 
> > Cc: Mike Turquette <mturquette@linaro.org>
> > Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
> > Signed-off-by: Joseph Lo <josephl@nvidia.com>
> > ---
> > This patch depends on the patch series "[PATCH 0/5] Tegra124 clock support"
> > that sent by Peter on 10/4/2013.
> 
> Uggh. This series mixes patches for drivers/clk and arch/arm/mach-tegra.
> I don't want to introduce dependencies between those two subsystems.
> Instead, if this patch is applied to the clock tree, and the reset of
> the patches to the Tegra tree, will that cause any build issues, or any
> run-time for any SoC other than Tegra124 (which is a new feature so it's
> fine if it doesn't work until everything is merged together)?

This patch can go through the clock tree and won't cause any build
issues or run-time failure even on Tegra124 (except CPU hot plug stress
testing). Only some warning message would show up.

But I am going to send some other patches for platform suspend support
for Tegra124, it might meet the issue you mentioned here. We only can
test it in our local tree or wait for the next linux-next (20131028?)
for testing after everything merged. So it might be OK, I guess.

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diff mbox

Patch

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 26ba059..c1c9330 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -106,6 +106,9 @@ 
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE	BIT(1)
 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL	BIT(0)
 
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS	0x470
+
 static void __iomem *clk_base;
 static void __iomem *pmc_base;
 
@@ -1120,6 +1123,27 @@  static void __init tegra124_pll_init(void __iomem *clk_base,
 
 }
 
+/* Tegra124 CPU clock and reset control functions */
+static void tegra124_wait_cpu_in_reset(u32 cpu)
+{
+	unsigned int reg;
+
+	do {
+		reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+		cpu_relax();
+	} while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+}
+
+static void tegra124_disable_cpu_clock(u32 cpu)
+{
+	/* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra124_cpu_car_ops = {
+	.wait_for_reset	= tegra124_wait_cpu_in_reset,
+	.disable_clock	= tegra124_disable_cpu_clock,
+};
+
 static const struct of_device_id pmc_match[] __initconst = {
 	{ .compatible = "nvidia,tegra124-pmc" },
 	{},
@@ -1202,5 +1226,7 @@  static void __init tegra124_clock_init(struct device_node *np)
 	tegra_add_of_provider(np);
 
 	tegra_clk_apply_init_table = tegra124_clock_apply_init_table;
+
+	tegra_cpu_car_ops = &tegra124_cpu_car_ops;
 }
 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);