From patchwork Fri Oct 4 16:37:14 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 280670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5D0BB2C008A for ; Sat, 5 Oct 2013 02:38:26 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755033Ab3JDQhh (ORCPT ); Fri, 4 Oct 2013 12:37:37 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:12666 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754792Ab3JDQhe (ORCPT ); Fri, 4 Oct 2013 12:37:34 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Fri, 04 Oct 2013 09:37:17 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 04 Oct 2013 09:33:34 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 04 Oct 2013 09:33:34 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.327.1; Fri, 4 Oct 2013 09:37:32 -0700 From: Alexandre Courbot To: Russell King , Stephen Warren , Tomasz Figa , Dave Martin , Olof Johansson , Arnd Bergmann , Kevin Hilman CC: , , , , , Alexandre Courbot Subject: [PATCH v7 4/5] ARM: tegra: set CPU reset handler with firmware op Date: Fri, 4 Oct 2013 09:37:14 -0700 Message-ID: <1380904635-18113-5-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1380904635-18113-1-git-send-email-acourbot@nvidia.com> References: <1380904635-18113-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use a firmware operation to set the CPU reset handler and only resort to doing it ourselves if there is none defined. This supports the booting of secondary CPUs on devices using a TrustZone secure monitor. Signed-off-by: Alexandre Courbot Reviewed-by: Tomasz Figa Reviewed-by: Stephen Warren --- arch/arm/mach-tegra/reset.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index e282395..368af0a 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -21,6 +21,7 @@ #include #include +#include #include "iomap.h" #include "irammap.h" @@ -65,6 +66,7 @@ static void __init tegra_cpu_reset_handler_enable(void) void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); const u32 reset_address = TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset; + int err; BUG_ON(is_enabled); BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); @@ -72,9 +74,18 @@ static void __init tegra_cpu_reset_handler_enable(void) memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, tegra_cpu_reset_handler_size); - tegra_cpu_reset_handler_set(reset_address); - - is_enabled = true; + err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); + switch (err) { + case -ENOSYS: + tegra_cpu_reset_handler_set(reset_address); + /* pass-through */ + case 0: + is_enabled = true; + break; + default: + pr_crit("Cannot set CPU reset handler: %d\n", err); + BUG(); + } } void __init tegra_cpu_reset_handler_init(void)