From patchwork Wed Jun 26 09:28:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 254670 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id CEF2A2C0095 for ; Wed, 26 Jun 2013 19:29:38 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751794Ab3FZJ3b (ORCPT ); Wed, 26 Jun 2013 05:29:31 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3810 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751786Ab3FZJ33 (ORCPT ); Wed, 26 Jun 2013 05:29:29 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 26 Jun 2013 02:29:02 -0700 Received: from hqemhub02.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 26 Jun 2013 02:27:26 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 26 Jun 2013 02:27:26 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Wed, 26 Jun 2013 02:29:29 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 26 Jun 2013 02:29:28 -0700 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r5Q9SmR5017123; Wed, 26 Jun 2013 02:29:27 -0700 (PDT) From: Hiroshi Doyu To: CC: , , Hiroshi Doyu Subject: [PATCH 20/23] iommu/tegra: smmu: Use dt-bindings MACRO Date: Wed, 26 Jun 2013 12:28:23 +0300 Message-ID: <1372238906-9346-21-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Use dt-bindings MACRO instead of SoC dependent MACROs. Signed-off-by: Hiroshi Doyu --- drivers/iommu/tegra-smmu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index ae71721..50eb843 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -41,6 +41,8 @@ #include #include +#include + /* bitmap of the page sizes currently supported */ #define SMMU_IOMMU_PGSIZES (SZ_4K) @@ -747,7 +749,7 @@ static int smmu_iommu_attach_dev(struct iommu_domain *domain, * Reserve "page zero" for AVP vectors using a common dummy * page. */ - if (map & HWG_AVPC) { + if (map & SWGID(AVPC)) { struct page *page; page = as->smmu->avp_vector_page;