From patchwork Tue Jun 4 10:47:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 248527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 76C342C0079 for ; Tue, 4 Jun 2013 20:47:51 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751415Ab3FDKrv (ORCPT ); Tue, 4 Jun 2013 06:47:51 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5934 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751173Ab3FDKru (ORCPT ); Tue, 4 Jun 2013 06:47:50 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 04 Jun 2013 03:47:50 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 04 Jun 2013 03:47:15 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 04 Jun 2013 03:47:15 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Tue, 4 Jun 2013 03:47:49 -0700 From: Joseph Lo To: Stephen Warren CC: , , Joseph Lo Subject: [PATCH V2 3/4] ARM: tegra: cpuidle: using IS_ENABLED for multi SoCs management in init func Date: Tue, 4 Jun 2013 18:47:34 +0800 Message-ID: <1370342855-32705-4-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.3 In-Reply-To: <1370342855-32705-1-git-send-email-josephl@nvidia.com> References: <1370342855-32705-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Clean up the Tegra CPUidle init function by using IS_ENABLED for multi SoCs management in the init function. Signed-off-by: Joseph Lo --- V2: * fix the coding style of the runtime chip selection --- arch/arm/mach-tegra/cpuidle.c | 11 ++++++----- arch/arm/mach-tegra/cpuidle.h | 17 +---------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 4a7a788..e85973c 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c @@ -31,15 +31,16 @@ void __init tegra_cpuidle_init(void) { switch (tegra_chip_id) { case TEGRA20: - tegra20_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) + tegra20_cpuidle_init(); break; case TEGRA30: - tegra30_cpuidle_init(); + if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) + tegra30_cpuidle_init(); break; case TEGRA114: - tegra114_cpuidle_init(); - break; - default: + if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC)) + tegra114_cpuidle_init(); break; } } diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 9bcf61f..9ec2c1a 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -17,25 +17,10 @@ #ifndef __MACH_TEGRA_CPUIDLE_H #define __MACH_TEGRA_CPUIDLE_H -#ifdef CONFIG_ARCH_TEGRA_2x_SOC +#ifdef CONFIG_CPU_IDLE int tegra20_cpuidle_init(void); -#else -static inline int tegra20_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_3x_SOC int tegra30_cpuidle_init(void); -#else -static inline int tegra30_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_ARCH_TEGRA_114_SOC int tegra114_cpuidle_init(void); -#else -static inline int tegra114_cpuidle_init(void) { return -ENODEV; } -#endif - -#ifdef CONFIG_CPU_IDLE void tegra_cpuidle_init(void); #else static inline void tegra_cpuidle_init(void) {}