From patchwork Fri Mar 22 11:54:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 229972 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6FFC32C00C2 for ; Fri, 22 Mar 2013 22:55:44 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933182Ab3CVLzn (ORCPT ); Fri, 22 Mar 2013 07:55:43 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:13862 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932939Ab3CVLzm (ORCPT ); Fri, 22 Mar 2013 07:55:42 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Fri, 22 Mar 2013 04:55:32 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 22 Mar 2013 04:55:31 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 22 Mar 2013 04:55:31 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Fri, 22 Mar 2013 04:55:34 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 22 Mar 2013 04:55:34 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r2MBtVCg008361; Fri, 22 Mar 2013 04:55:32 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver CC: , Stephen Warren , Prashant Gaikwad , Mike Turquette , Thierry Reding , , Subject: [PATCH] clk: tegra: Don't enable PLLs during early boot Date: Fri, 22 Mar 2013 13:54:58 +0200 Message-ID: <1363953308-28828-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The PLL code relies on udelay() which is not available when CCF is initialized. Hence we can't enable any PLL during this phase. Signed-off-by: Peter De Schrijver --- Stephen, Can you confirm this is ok for the audio drivers? We used to be lucky that this has worked up to now, but I will introduce some changes to the pll lock check code which cause this to fail due to the slight differences in timing. --- drivers/clk/tegra/clk-tegra20.c | 4 ++-- drivers/clk/tegra/clk-tegra30.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index b92d48b..7cc76b0 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1230,8 +1230,8 @@ static __initdata struct tegra_clk_init_table init_table[] = { {usbd, clk_max, 12000000, 0}, {usb2, clk_max, 12000000, 0}, {usb3, clk_max, 12000000, 0}, - {pll_a, clk_max, 56448000, 1}, - {pll_a_out0, clk_max, 11289600, 1}, + {pll_a, clk_max, 56448000, 0}, + {pll_a_out0, clk_max, 11289600, 0}, {cdev1, clk_max, 0, 1}, {blink, clk_max, 32768, 1}, {i2s1, pll_a_out0, 11289600, 0}, diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index ba6f51b..b705408 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1882,11 +1882,11 @@ static __initdata struct tegra_clk_init_table init_table[] = { {uartc, pll_p, 408000000, 0}, {uartd, pll_p, 408000000, 0}, {uarte, pll_p, 408000000, 0}, - {pll_a, clk_max, 564480000, 1}, - {pll_a_out0, clk_max, 11289600, 1}, - {extern1, pll_a_out0, 0, 1}, + {pll_a, clk_max, 564480000, 0}, + {pll_a_out0, clk_max, 11289600, 0}, + {extern1, pll_a_out0, 0, 0}, {clk_out_1_mux, extern1, 0, 0}, - {clk_out_1, clk_max, 0, 1}, + {clk_out_1, clk_max, 0, 0}, {blink, clk_max, 0, 1}, {i2s0, pll_a_out0, 11289600, 0}, {i2s1, pll_a_out0, 11289600, 0},