From patchwork Fri Mar 8 14:00:45 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 226129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6D7A42C03BD for ; Sat, 9 Mar 2013 01:02:37 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932686Ab3CHOCg (ORCPT ); Fri, 8 Mar 2013 09:02:36 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:12445 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932413Ab3CHOCf (ORCPT ); Fri, 8 Mar 2013 09:02:35 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 08 Mar 2013 06:07:35 -0800 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 08 Mar 2013 05:56:16 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 08 Mar 2013 05:56:16 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server id 8.3.298.1; Fri, 8 Mar 2013 06:02:27 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Fri, 08 Mar 2013 06:02:28 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r28E2Pw6012348; Fri, 8 Mar 2013 06:02:26 -0800 (PST) From: Laxman Dewangan To: CC: , , , Laxman Dewangan Subject: [PATCH] ARM: DT: tegra20/tegra30: Correct clock id for UARTB Date: Fri, 8 Mar 2013 19:30:45 +0530 Message-ID: <1362751245-32432-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org UARTB clock bit in CAR register is 7. Correcting this in DTS file. Signed-off-by: Laxman Dewangan --- arch/arm/boot/dts/tegra20.dtsi | 2 +- arch/arm/boot/dts/tegra30.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index bbbe2de..b89fea2 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -260,7 +260,7 @@ reg-shift = <2>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 96>; + clocks = <&tegra_car 7>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index eddd0f9..0c9532b 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -247,7 +247,7 @@ reg-shift = <2>; interrupts = <0 37 0x04>; nvidia,dma-request-selector = <&apbdma 9>; - clocks = <&tegra_car 160>; + clocks = <&tegra_car 7>; status = "disabled"; };