From patchwork Fri Jan 4 11:04:01 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 209443 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B44232C007B for ; Fri, 4 Jan 2013 22:05:01 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754607Ab3ADLEq (ORCPT ); Fri, 4 Jan 2013 06:04:46 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:8210 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753454Ab3ADLEo (ORCPT ); Fri, 4 Jan 2013 06:04:44 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Fri, 04 Jan 2013 03:08:17 -0800 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 04 Jan 2013 03:04:24 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 04 Jan 2013 03:04:24 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.279.1; Fri, 4 Jan 2013 03:04:22 -0800 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw02.nvidia.com with MailMarshal (v6,7,2,8378) id ; Fri, 04 Jan 2013 03:04:22 -0800 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r04B4GPJ029803; Fri, 4 Jan 2013 03:04:17 -0800 (PST) From: Laxman Dewangan To: CC: , , , , Laxman Dewangan Subject: [PATCH] ARM: DT: tegra: add DT entry for KBC controller Date: Fri, 4 Jan 2013 16:34:01 +0530 Message-ID: <1357297442-28952-1-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan --- arch/arm/boot/dts/tegra20.dtsi | 7 +++++++ arch/arm/boot/dts/tegra30.dtsi | 7 +++++++ 2 files changed, 14 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index fe35c72..133d00d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -352,6 +352,13 @@ status = "disabled"; }; + kbc { + compatible = "nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc"; reg = <0x7000e400 0x400>; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index f534a50..bc9f702 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -368,6 +368,13 @@ status = "disabled"; }; + kbc { + compatible = "nvidia,tegra30-kbc", nvidia,tegra20-kbc"; + reg = <0x7000e200 0x100>; + interrupts = <0 85 0x04>; + status = "disabled"; + }; + pmc { compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; reg = <0x7000e400 0x400>;