| Message ID | 1349691981-31038-5-git-send-email-josephl@nvidia.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On 10/08/2012 04:26 AM, Joseph Lo wrote: > Enable csite (debug and trace controller) clock at init to prevent it > be disabled. And this also the necessary clock for CPU be brought up or > resumed from a power-gate low power state (e.g., LP2). Does it make sense to enable this clock only when entering LP2? Or do we really need to keep it on 100% of the time? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Wed, 2012-10-10 at 06:38 +0800, Stephen Warren wrote: > On 10/08/2012 04:26 AM, Joseph Lo wrote: > > Enable csite (debug and trace controller) clock at init to prevent it > > be disabled. And this also the necessary clock for CPU be brought up or > > resumed from a power-gate low power state (e.g., LP2). > > Does it make sense to enable this clock only when entering LP2? Or do we > really need to keep it on 100% of the time? Hmmm. I am not sure does the RealView or Lauterbach ICE can still attach to the target if the clock is not available. Or even it can be attached but some functions of the debugger may not work. Because the CoreSight is a very fancy debug module. I only test it with a light weight debugger (OpenOCD). It still can work without turning on the CoreSight clock. Maybe it just because the openocd debugger only using the jtag interface. Anyway, I think we need the csite always on for the developer that using RealView or Lauterbach ICE. Thanks, Joseph -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0b0a5f5..4a2dd98 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -104,6 +104,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, + { "csite", NULL, 0, true }, { NULL, NULL, 0, 0}, }; #endif
Enable csite (debug and trace controller) clock at init to prevent it be disabled. And this also the necessary clock for CPU be brought up or resumed from a power-gate low power state (e.g., LP2). Signed-off-by: Joseph Lo <josephl@nvidia.com> --- arch/arm/mach-tegra/common.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)