From patchwork Wed Jul 25 15:06:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 173194 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 714A52C00A1 for ; Thu, 26 Jul 2012 01:06:27 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964778Ab2GYPGZ (ORCPT ); Wed, 25 Jul 2012 11:06:25 -0400 Received: from moutng.kundenserver.de ([212.227.17.9]:64053 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964773Ab2GYPGY (ORCPT ); Wed, 25 Jul 2012 11:06:24 -0400 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap3) with ESMTP (Nemesis) id 0M1XmT-1TnWCL2YYL-00tUq5; Wed, 25 Jul 2012 17:06:20 +0200 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 1E98F2A280ED; Wed, 25 Jul 2012 17:06:20 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nmADZ0MGj47j; Wed, 25 Jul 2012 17:06:18 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 8A8B52A2830F; Wed, 25 Jul 2012 17:06:17 +0200 (CEST) From: Thierry Reding To: Stephen Warren Cc: Olof Johansson , Colin Cross , linux-tegra@vger.kernel.org Subject: [PATCH 3/3] ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support Date: Wed, 25 Jul 2012 17:06:15 +0200 Message-Id: <1343228775-1330-3-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.11.2 In-Reply-To: <1343228775-1330-1-git-send-email-thierry.reding@avionic-design.de> References: <1343228775-1330-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:HUMBfo2Xqb8yZX/sH+dafdvzD0TDdQre6W4zRrrqYP0 dJv2/1LpDNF8C92PpZc/bcB+Ks8/BU7MdO5aiF57QuusrV8SJJ a8yjp4BI7+ARMP2o9tb0lIwMN9VPD37853rzYJQ6AHHTJmB+Lj RORIT6Ifw4He0G2QVfaEeXAWxwHSfIf8yHHiuVCmTZtTK8Z11J GSy9HaJkWeivFkGdXyd+0wG/BaY+O/j2A+S5O/hKwo+vmExnjF 78o1qCi9qnazLuLIuthZfxLYPlPJvkFHRiQvRQFmEaejn5rNzs U9pmDsMSJZTOdnCWYbmexnFFOGW97fMxaUddS8N1ZcRi/qxekW f0LqLQBlFQxasbBFSnpLnPCgf6Y21JRq1j9k2iUI++V00Qq+hr G0/GH2TFhUfCoIaQkXgALEGni5BxJXtsR8JzCmbIPtM0Lsrjve yAhGc Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tamonten Evaluation Carrier is an evaluation board for the Tamonten SOM. More information is available here: http://www.avionic-design.de/en/products/nvidia-tegra-tamonten-system-en/nvidia-tegra-tamonten-evboard-en.html Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra20-tec.dts | 490 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-tegra/Makefile.boot | 1 + 2 files changed, 491 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-tec.dts diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts new file mode 100644 index 0000000..473a320 --- /dev/null +++ b/arch/arm/boot/dts/tegra20-tec.dts @@ -0,0 +1,490 @@ +/dts-v1/; + +/include/ "tegra20.dtsi" + +/ { + model = "Avionic Design Tamonten Evaluation Carrier"; + compatible = "ad,tec", "nvidia,tegra20"; + + memory { + reg = <0x00000000 0x20000000>; + }; + + pinmux { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + ata { + nvidia,pins = "ata"; + nvidia,function = "ide"; + }; + atb { + nvidia,pins = "atb", "gma", "gme"; + nvidia,function = "sdio4"; + }; + atc { + nvidia,pins = "atc"; + nvidia,function = "nand"; + }; + atd { + nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu", + "spia", "spib", "spic"; + nvidia,function = "gmi"; + }; + cdev1 { + nvidia,pins = "cdev1"; + nvidia,function = "plla_out"; + }; + cdev2 { + nvidia,pins = "cdev2"; + nvidia,function = "pllp_out4"; + }; + crtp { + nvidia,pins = "crtp"; + nvidia,function = "crt"; + }; + csus { + nvidia,pins = "csus"; + nvidia,function = "vi_sensor_clk"; + }; + dap1 { + nvidia,pins = "dap1"; + nvidia,function = "dap1"; + }; + dap2 { + nvidia,pins = "dap2"; + nvidia,function = "dap2"; + }; + dap3 { + nvidia,pins = "dap3"; + nvidia,function = "dap3"; + }; + dap4 { + nvidia,pins = "dap4"; + nvidia,function = "dap4"; + }; + ddc { + nvidia,pins = "ddc"; + nvidia,function = "i2c2"; + }; + dta { + nvidia,pins = "dta", "dtd"; + nvidia,function = "sdio2"; + }; + dtb { + nvidia,pins = "dtb", "dtc", "dte"; + nvidia,function = "rsvd1"; + }; + dtf { + nvidia,pins = "dtf"; + nvidia,function = "i2c3"; + }; + gmc { + nvidia,pins = "gmc"; + nvidia,function = "uartd"; + }; + gpu7 { + nvidia,pins = "gpu7"; + nvidia,function = "rtck"; + }; + gpv { + nvidia,pins = "gpv", "slxa", "slxk"; + nvidia,function = "pcie"; + }; + hdint { + nvidia,pins = "hdint", "pta"; + nvidia,function = "hdmi"; + }; + i2cp { + nvidia,pins = "i2cp"; + nvidia,function = "i2cp"; + }; + irrx { + nvidia,pins = "irrx", "irtx"; + nvidia,function = "uarta"; + }; + kbca { + nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", + "kbce", "kbcf"; + nvidia,function = "kbc"; + }; + lcsn { + nvidia,pins = "lcsn", "ld0", "ld1", "ld2", + "ld3", "ld4", "ld5", "ld6", "ld7", + "ld8", "ld9", "ld10", "ld11", "ld12", + "ld13", "ld14", "ld15", "ld16", "ld17", + "ldc", "ldi", "lhp0", "lhp1", "lhp2", + "lhs", "lm0", "lm1", "lpp", "lpw0", + "lpw1", "lpw2", "lsc0", "lsc1", "lsck", + "lsda", "lsdi", "lspi", "lvp0", "lvp1", + "lvs"; + nvidia,function = "displaya"; + }; + owc { + nvidia,pins = "owc", "spdi", "spdo", "uac"; + nvidia,function = "rsvd2"; + }; + pmc { + nvidia,pins = "pmc"; + nvidia,function = "pwr_on"; + }; + rm { + nvidia,pins = "rm"; + nvidia,function = "i2c1"; + }; + sdb { + nvidia,pins = "sdb", "sdc", "sdd"; + nvidia,function = "pwm"; + }; + sdio1 { + nvidia,pins = "sdio1"; + nvidia,function = "sdio1"; + }; + slxc { + nvidia,pins = "slxc", "slxd"; + nvidia,function = "spdif"; + }; + spid { + nvidia,pins = "spid", "spie", "spif"; + nvidia,function = "spi1"; + }; + spig { + nvidia,pins = "spig", "spih"; + nvidia,function = "spi2_alt"; + }; + uaa { + nvidia,pins = "uaa", "uab", "uda"; + nvidia,function = "ulpi"; + }; + uad { + nvidia,pins = "uad"; + nvidia,function = "irda"; + }; + uca { + nvidia,pins = "uca", "ucb"; + nvidia,function = "uartc"; + }; + conf_ata { + nvidia,pins = "ata", "atb", "atc", "atd", "ate", + "cdev1", "cdev2", "dap1", "dtb", "gma", + "gmb", "gmc", "gmd", "gme", "gpu7", + "gpv", "i2cp", "pta", "rm", "slxa", + "slxk", "spia", "spib", "uac"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + conf_ck32 { + nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", + "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; + nvidia,pull = <0>; + }; + conf_csus { + nvidia,pins = "csus", "spid", "spif"; + nvidia,pull = <1>; + nvidia,tristate = <1>; + }; + conf_crtp { + nvidia,pins = "crtp", "dap2", "dap3", "dap4", + "dtc", "dte", "dtf", "gpu", "sdio1", + "slxc", "slxd", "spdi", "spdo", "spig", + "uda"; + nvidia,pull = <0>; + nvidia,tristate = <1>; + }; + conf_ddc { + nvidia,pins = "ddc", "dta", "dtd", "kbca", + "kbcb", "kbcc", "kbcd", "kbce", "kbcf", + "sdc"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; + conf_hdint { + nvidia,pins = "hdint", "lcsn", "ldc", "lm1", + "lpw1", "lsc1", "lsck", "lsda", "lsdi", + "lvp0", "owc", "sdb"; + nvidia,tristate = <1>; + }; + conf_irrx { + nvidia,pins = "irrx", "irtx", "sdd", "spic", + "spie", "spih", "uaa", "uab", "uad", + "uca", "ucb"; + nvidia,pull = <2>; + nvidia,tristate = <1>; + }; + conf_lc { + nvidia,pins = "lc", "ls"; + nvidia,pull = <2>; + }; + conf_ld0 { + nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", + "ld5", "ld6", "ld7", "ld8", "ld9", + "ld10", "ld11", "ld12", "ld13", "ld14", + "ld15", "ld16", "ld17", "ldi", "lhp0", + "lhp1", "lhp2", "lhs", "lm0", "lpp", + "lpw0", "lpw2", "lsc0", "lspi", "lvp1", + "lvs", "pmc"; + nvidia,tristate = <0>; + }; + conf_ld17_0 { + nvidia,pins = "ld17_0", "ld19_18", "ld21_20", + "ld23_22"; + nvidia,pull = <1>; + }; + }; + }; + + i2s@70002800 { + status = "okay"; + }; + + serial@70006300 { + clock-frequency = <216000000>; + status = "okay"; + }; + + i2c@7000c000 { + clock-frequency = <400000>; + status = "okay"; + + wm8903: wm8903@1a { + compatible = "wlf,wm8903"; + reg = <0x1a>; + interrupt-parent = <&gpio>; + interrupts = <187 0x04>; + + gpio-controller; + #gpio-cells = <2>; + + micdet-cfg = <0>; + micdet-delay = <100>; + gpio-cfg = <0xffffffff + 0xffffffff + 0 + 0xffffffff + 0xffffffff>; + }; + }; + + i2c@7000d000 { + clock-frequency = <400000>; + status = "okay"; + + pmu: tps6586x@34 { + compatible = "ti,tps6586x"; + reg = <0x34>; + interrupts = <0 86 0x4>; + + #gpio-cells = <2>; + gpio-controller; + + sm0-supply = <&vdd_sys_sm0>; + sm1-supply = <&vdd_sys_sm1>; + sm2-supply = <&vdd_sys_sm2>; + vinldo01-supply = <&sm2>; + vinldo23-supply = <&sm2>; + vinldo4-supply = <&sm2>; + vinldo678-supply = <&sm2>; + vinldo9-supply = <&sm2>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + sm0: regulator@0 { + reg = <0>; + regulator-compatible = "sm0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + sm1: regulator@1 { + reg = <1>; + regulator-compatible = "sm1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + sm2: regulator@2 { + reg = <2>; + regulator-compatible = "sm2"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo0: regulator@3 { + reg = <3>; + regulator-compatible = "ldo0"; + regulator-name = "PCIE CLK"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo1: regulator@4 { + reg = <4>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + ldo2: regulator@5 { + reg = <5>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3: regulator@6 { + reg = <6>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + ldo4: regulator@7 { + reg = <7>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5: regulator@8 { + reg = <8>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + ldo6: regulator@9 { + reg = <9>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo7: regulator@10 { + reg = <10>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8: regulator@11 { + reg = <11>; + regulator-compatible = "ldo8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo9: regulator@12 { + reg = <12>; + regulator-compatible = "ldo9"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + }; + }; + }; + + pmc { + nvidia,invert-interrupt; + }; + + usb@c5008000 { + status = "okay"; + }; + + sdhci@c8000600 { + cd-gpios = <&gpio 58 0>; /* gpio PH2 */ + wp-gpios = <&gpio 59 0>; /* gpio PH3 */ + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + #address-cells = <1>; + #size-cells = <1>; + + vdd_sys_sm0: regulator@0 { + compatible = "regulator-fixed"; + reg = <0 1>; + + regulator-name = "VDD_SYS_SM0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sys_sm1: regulator@1 { + compatible = "regulator-fixed"; + reg = <1 1>; + + regulator-name = "VDD_SYS_SM1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_sys_sm2: regulator@2 { + compatible = "regulator-fixed"; + reg = <2 1>; + + regulator-name = "VDD_SYS_SM2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + pci_vdd_reg: regulator@3 { + compatible = "regulator-fixed"; + reg = <3 1>; + + regulator-name = "PCIE VDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + + enable-active-high; + gpio = <&pmu 2 0>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-wm8903-harmony", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Avionic Design Tamonten Evaluation Carrier"; + + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "ROP", + "Int Spk", "RON", + "Int Spk", "LOP", + "Int Spk", "LON", + "Mic Jack", "MICBIAS", + "IN1L", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 0>; + nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */ + nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */ + nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */ + }; +}; diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot index 84757e0..cb8f649 100644 --- a/arch/arm/mach-tegra/Makefile.boot +++ b/arch/arm/mach-tegra/Makefile.boot @@ -10,4 +10,5 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-plutux.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-medcom.dtb +dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-tec.dtb dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb