From patchwork Wed Jul 4 09:34:47 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 168939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2EADB2C00E7 for ; Wed, 4 Jul 2012 19:38:05 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756634Ab2GDJhH (ORCPT ); Wed, 4 Jul 2012 05:37:07 -0400 Received: from hqemgate03.nvidia.com ([216.228.121.140]:3965 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756534Ab2GDJhF (ORCPT ); Wed, 4 Jul 2012 05:37:05 -0400 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Wed, 04 Jul 2012 02:37:00 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Wed, 04 Jul 2012 02:36:43 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Wed, 04 Jul 2012 02:36:43 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.264.0; Wed, 4 Jul 2012 02:36:42 -0700 Received: from tegra-chromium-2.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server id 8.3.264.0; Wed, 4 Jul 2012 17:36:39 +0800 From: Wei Ni To: , , CC: , , , , , , , , Wei Ni Subject: [PATCH 4/5] ARM: dt: t30 cardhu: add pinmux, gpio for wlan Date: Wed, 4 Jul 2012 17:34:47 +0800 Message-ID: <1341394488-13169-5-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1341394488-13169-1-git-send-email-wni@nvidia.com> References: <1341394488-13169-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This adds wlan pinmux and gpio settings to the Tegra30 Cardhu device tree. Signed-off-by: Wei Ni --- arch/arm/boot/dts/tegra30-cardhu.dts | 30 ++++++++++++++++++++++++++++++ 1 files changed, 30 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/tegra30-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts index c169bce..08749cc 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dts +++ b/arch/arm/boot/dts/tegra30-cardhu.dts @@ -31,6 +31,22 @@ nvidia,pull = <2>; nvidia,tristate = <0>; }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,pull = <0>; + nvidia,tristate = <0>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4"; + nvidia,function = "sdmmc3"; + nvidia,pull = <2>; + nvidia,tristate = <0>; + }; sdmmc4_clk_pcc4 { nvidia,pins = "sdmmc4_clk_pcc4", "sdmmc4_rst_n_pcc3"; @@ -60,6 +76,15 @@ nvidia,pull = <0>; nvidia,tristate = <0>; }; + sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <0>; + nvidia,schmitt = <0>; + nvidia,pull-down-strength = <46>; + nvidia,pull-up-strength = <42>; + nvidia,slew-rate-rising = <1>; + nvidia,slew-rate-falling = <1>; + }; }; }; @@ -142,6 +167,11 @@ bus-width = <4>; }; + sdhci@78000400 { + status = "okay"; + power-gpios = <&gpio 28 0>; /* gpio PD4 */ + }; + sdhci@78000600 { status = "okay"; bus-width = <8>;