From patchwork Wed Jul 4 09:34:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 168936 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E8EF22C00E7 for ; Wed, 4 Jul 2012 19:37:07 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753541Ab2GDJhG (ORCPT ); Wed, 4 Jul 2012 05:37:06 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:1094 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755467Ab2GDJhE (ORCPT ); Wed, 4 Jul 2012 05:37:04 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 04 Jul 2012 02:35:55 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 04 Jul 2012 02:36:39 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 04 Jul 2012 02:36:39 -0700 Received: from hkemhub02.nvidia.com (10.18.67.13) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.264.0; Wed, 4 Jul 2012 02:36:39 -0700 Received: from tegra-chromium-2.nvidia.com (10.18.67.5) by hkemhub02.nvidia.com (10.18.67.13) with Microsoft SMTP Server id 8.3.264.0; Wed, 4 Jul 2012 17:36:36 +0800 From: Wei Ni To: , , CC: , , , , , , , , Wei Ni Subject: [PATCH 1/5] ARM: tegra: set up wlan clocks for tegra dt Date: Wed, 4 Jul 2012 17:34:44 +0800 Message-ID: <1341394488-13169-2-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1341394488-13169-1-git-send-email-wni@nvidia.com> References: <1341394488-13169-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Set up the wlan clock tree for Tegra20 and Tegra30. Signed-off-by: Wei Ni --- arch/arm/mach-tegra/board-dt-tegra20.c | 1 + arch/arm/mach-tegra/board-dt-tegra30.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c index 70a19a9..fbcc7d9 100644 --- a/arch/arm/mach-tegra/board-dt-tegra20.c +++ b/arch/arm/mach-tegra/board-dt-tegra20.c @@ -78,6 +78,7 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a", "pll_p_out1", 56448000, true }, { "pll_a_out0", "pll_a", 11289600, true }, { "cdev1", NULL, 0, true }, + { "blink", "clk_32k", 32768, true }, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false}, { NULL, NULL, 0, 0}, diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c index 53bf60f..2d73c61 100644 --- a/arch/arm/mach-tegra/board-dt-tegra30.c +++ b/arch/arm/mach-tegra/board-dt-tegra30.c @@ -61,6 +61,7 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { { "pll_a_out0", "pll_a", 11289600, true }, { "extern1", "pll_a_out0", 0, true }, { "clk_out_1", "extern1", 0, true }, + { "blink", "clk_32k", 32768, true }, { "i2s0", "pll_a_out0", 11289600, false}, { "i2s1", "pll_a_out0", 11289600, false}, { "i2s2", "pll_a_out0", 11289600, false},