From patchwork Wed Jun 13 10:12:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 164614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 781B4B6FF4 for ; Wed, 13 Jun 2012 20:24:47 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753016Ab2FMKW7 (ORCPT ); Wed, 13 Jun 2012 06:22:59 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:6067 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753019Ab2FMKW2 (ORCPT ); Wed, 13 Jun 2012 06:22:28 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 13 Jun 2012 03:21:04 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 13 Jun 2012 03:21:51 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 13 Jun 2012 03:21:51 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.245.1; Wed, 13 Jun 2012 03:21:51 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Wed, 13 Jun 2012 03:21:51 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q5DALbJt011219; Wed, 13 Jun 2012 03:21:48 -0700 (PDT) From: Laxman Dewangan To: , , , , CC: , , , Laxman Dewangan Subject: [PATCH V3 1/4] i2c: tegra: make sure register writes completes Date: Wed, 13 Jun 2012 15:42:36 +0530 Message-ID: <1339582359-7911-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1339582359-7911-1-git-send-email-ldewangan@nvidia.com> References: <1339582359-7911-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra PPSB (an peripheral bus) queues writes transactions. In order to guarantee that writes have completed before a certain time, a read transaction to a register on the same bus must be executed. This is necessary in situations such as when clearing an interrupt status or enable, so that when returning from an interrupt handler, the HW has already de-asserted its interrupt status output, which will avoid spurious interrupts. Signed-off-by: Laxman Dewangan --- Changes from V1: - Using the readback for mask/unmask of irq also. Changes from V2: - Read back is done whenever write happen in i2c register other than TX FIFO. drivers/i2c/busses/i2c-tegra.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 8b2e555..785f7f7 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -165,6 +165,10 @@ static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg) { writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); + + /* Read back register to make sure that register writes completed */ + if (reg != I2C_TX_FIFO) + readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); } static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)