From patchwork Tue Jun 12 10:37:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 164381 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 08B65B6FA9 for ; Tue, 12 Jun 2012 20:47:19 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751766Ab2FLKrS (ORCPT ); Tue, 12 Jun 2012 06:47:18 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:2016 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751035Ab2FLKrQ (ORCPT ); Tue, 12 Jun 2012 06:47:16 -0400 Received: from hqnvupgp05.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 12 Jun 2012 03:45:57 -0700 Received: from hqemhub03.nvidia.com ([172.17.108.22]) by hqnvupgp05.nvidia.com (PGP Universal service); Tue, 12 Jun 2012 03:46:44 -0700 X-PGP-Universal: processed; by hqnvupgp05.nvidia.com on Tue, 12 Jun 2012 03:46:44 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.245.1; Tue, 12 Jun 2012 03:46:44 -0700 Received: from daphne.nvidia.com (Not Verified[172.16.212.96]) by hqnvemgw01.nvidia.com with MailMarshal (v6,7,2,8378) id ; Tue, 12 Jun 2012 03:46:43 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q5CAkY72011877; Tue, 12 Jun 2012 03:46:40 -0700 (PDT) From: Laxman Dewangan To: , , , , CC: , , , Laxman Dewangan Subject: [PATCH V2 1/4] i2c: tegra: make sure register writes completes Date: Tue, 12 Jun 2012 16:07:28 +0530 Message-ID: <1339497451-26260-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1339497451-26260-1-git-send-email-ldewangan@nvidia.com> References: <1339497451-26260-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The Tegra PPSB (an peripheral bus) queues writes transactions. In order to guarantee that writes have completed before a certain time, a read transaction to a register on the same bus must be executed. This is necessary in situations such as when clearing an interrupt status or enable, so that when returning from an interrupt handler, the HW has already de-asserted its interrupt status output, which will avoid spurious interrupts. Signed-off-by: Laxman Dewangan --- changes from V1: Taken care of Wolfram's review comment. drivers/i2c/busses/i2c-tegra.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 3da7ee3..753519a 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -189,6 +189,9 @@ static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); int_mask &= ~mask; i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); + + /* Read back register to make sure that register writes completed */ + i2c_readl(i2c_dev, I2C_INT_MASK); } static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) @@ -196,6 +199,9 @@ static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask) u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK); int_mask |= mask; i2c_writel(i2c_dev, int_mask, I2C_INT_MASK); + + /* Read back register to make sure that register writes completed */ + i2c_readl(i2c_dev, I2C_INT_MASK); } static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev) @@ -430,6 +436,13 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id) if (i2c_dev->is_dvc) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); + /* + * Register write get queued in the PPSB bus and write can + * happen later. Read back register to make sure that register + * write is completed. + */ + i2c_readl(i2c_dev, I2C_INT_STATUS); + if (status & I2C_INT_PACKET_XFER_COMPLETE) { BUG_ON(i2c_dev->msg_buf_remaining); complete(&i2c_dev->msg_complete); @@ -444,6 +457,9 @@ err: if (i2c_dev->is_dvc) dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); + /* Read back register to make sure that register writes completed */ + i2c_readl(i2c_dev, I2C_INT_STATUS); + complete(&i2c_dev->msg_complete); return IRQ_HANDLED; }