From patchwork Wed Mar 28 14:33:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 149237 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 05ABEB6FAB for ; Thu, 29 Mar 2012 01:34:40 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758091Ab2C1Oei (ORCPT ); Wed, 28 Mar 2012 10:34:38 -0400 Received: from moutng.kundenserver.de ([212.227.17.10]:61685 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757145Ab2C1Oeh (ORCPT ); Wed, 28 Mar 2012 10:34:37 -0400 Received: from benhur.adnet.avionic-design.de (p548E1129.dip0.t-ipconnect.de [84.142.17.41]) by mrelayeu.kundenserver.de (node=mreu4) with ESMTP (Nemesis) id 0MR6eg-1RpIma3tRW-00UNmt; Wed, 28 Mar 2012 16:34:19 +0200 Received: from mailbox.adnet.avionic-design.de (add-virt-zarafa.adnet.avionic-design.de [172.20.129.9]) by benhur.adnet.avionic-design.de (Postfix) with ESMTP id 9B2692C4122; Wed, 28 Mar 2012 16:34:21 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id AA19E2920001; Wed, 28 Mar 2012 16:34:17 +0200 (CEST) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pt2egEzLWhUE; Wed, 28 Mar 2012 16:34:15 +0200 (CEST) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) (Authenticated sender: thierry.reding) by mailbox.adnet.avionic-design.de (Postfix) with ESMTPA id 627FE2920003; Wed, 28 Mar 2012 16:34:10 +0200 (CEST) From: Thierry Reding To: devicetree-discuss@lists.ozlabs.org Cc: Simon Que , Bill Huang , linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, Sascha Hauer , Arnd Bergmann , Matthias Kaehlcke , Kurt Van Dijck , Rob Herring , Grant Likely , Colin Cross , Olof Johansson , Stephen Warren , Richard Purdie , Mark Brown , Mitch Bradley , Mike Frysinger , Eric Miao , Lars-Peter Clausen , Ryan Mallon , Shawn Guo , Bernhard Walle Subject: [PATCH v5 06/16] ARM: tegra: Fix PWM clock programming Date: Wed, 28 Mar 2012 16:33:48 +0200 Message-Id: <1332945238-14897-7-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.7.9.4 In-Reply-To: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de> References: <1332945238-14897-1-git-send-email-thierry.reding@avionic-design.de> X-Provags-ID: V02:K0:vX5Kz2+GHOoRoZfe36OtORmr2J2NoqbVMUqy1sgVgRF /6+PDhHqfG627WY8gJq11w88td1L9GnuzXPJIcR9JAJR4zHSTS IbN6xmfF6dXbHKgFz59gIlkdSnt+dswHNGo5uVneKM6lgrkVgJ TeYzzh0FrY5Xqwd9JE45TXWvloO6UDDyiPrRYdsmiPZW3Igq8F l8uozbL+Xk7ED5RiLGuFJj3CVKrcXwksByKhawLg+tq5pjTpLE QpvDt108VIQDOzqcR0ZrFnucQaIWrJlE694BRBpPLH7nOOZG4B bN+kcZsnurLCoPb1NUZm0eMWbCpI45YhCU7HlVAnn3+KCNf6LA DJ+dUCVnvhrZR7EsycGtY81YMghUI9Vt5Ix80WjQVSrVtuZnVs nZeUZeb/ztQ20gVidT4Wbcwdp+t8fbkyAUDAQsa49GaLM2AIXn cYdzT Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Simon Que PWM clock source registers in Tegra 2 have different clock source selection bit fields than other registers. PWM clock source bits in CLK_SOURCE_PWM_0 register are located at bit field bit[30:28] while others are at bit field bit[31:30] in their respective clock source register. This patch updates the clock programming to correctly reflect that, by adding a flag to indicate the alternate bit field format and checking for it when selecting a clock source (parent clock). Signed-off-by: Bill Huang Signed-off-by: Simon Que Signed-off-by: Thierry Reding Acked-by: Stephen Warren --- Changes in v4: - reuse PWM flag from Tegra 30 clock programming - mask out bit 31 explicitly arch/arm/mach-tegra/tegra2_clocks.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 592a4ee..64735bd 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -69,6 +69,8 @@ #define PERIPH_CLK_SOURCE_MASK (3<<30) #define PERIPH_CLK_SOURCE_SHIFT 30 +#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28) +#define PERIPH_CLK_SOURCE_PWM_SHIFT 28 #define PERIPH_CLK_SOURCE_ENABLE (1<<28) #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF @@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c) u32 val = clk_readl(c->reg); const struct clk_mux_sel *mux = NULL; const struct clk_mux_sel *sel; + u32 shift; + u32 mask; + + if (c->flags & MUX_PWM) { + shift = PERIPH_CLK_SOURCE_PWM_SHIFT; + mask = PERIPH_CLK_SOURCE_PWM_MASK; + } else { + shift = PERIPH_CLK_SOURCE_SHIFT; + mask = PERIPH_CLK_SOURCE_MASK; + } + if (c->flags & MUX) { for (sel = c->inputs; sel->input != NULL; sel++) { - if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) + if ((val & mask) >> shift == sel->value) mux = sel; } BUG_ON(!mux); @@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) { u32 val; const struct clk_mux_sel *sel; + u32 mask, shift; + pr_debug("%s: %s %s\n", __func__, c->name, p->name); + + if (c->flags & MUX_PWM) { + shift = PERIPH_CLK_SOURCE_PWM_SHIFT; + mask = PERIPH_CLK_SOURCE_PWM_MASK; + } else { + shift = PERIPH_CLK_SOURCE_SHIFT; + mask = PERIPH_CLK_SOURCE_MASK; + } + for (sel = c->inputs; sel->input != NULL; sel++) { if (sel->input == p) { val = clk_readl(c->reg); - val &= ~PERIPH_CLK_SOURCE_MASK; - val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; + val &= ~mask; + val |= (sel->value) << shift; if (c->refcnt) clk_enable(p); @@ -2146,7 +2170,7 @@ static struct clk tegra_list_clks[] = { PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), - PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), + PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM), PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),